HSC-ADC-EVALB-DCZ Analog Devices Inc, HSC-ADC-EVALB-DCZ Datasheet - Page 14

KIT EVAL ADC FIFO DUAL-CH USB HS

HSC-ADC-EVALB-DCZ

Manufacturer Part Number
HSC-ADC-EVALB-DCZ
Description
KIT EVAL ADC FIFO DUAL-CH USB HS
Manufacturer
Analog Devices Inc
Datasheet

Specifications of HSC-ADC-EVALB-DCZ

Design Resources
Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003)
Accessory Type
ADC Interface Board
Silicon Manufacturer
Analog Devices
Application Sub Type
ADC
Kit Application Type
Data Converter
Features
Buffer Memory Board For Capturing Digital Data, USB Port Interface, Windows 98, Windows 2000
Kit Contents
ADC Analyzer, Buffer Memory Board
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
Dual ADC Version
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
HSC-ADC-EVALB-SC/HSC-ADC-EVALB-DC
FIFO SCHEMATICS AND PCB LAYOUT
SCHEMATICS
WRT_CLK1
R108
R109
DNP
DNP
VCC
E101
E102
D1_17
D1_16
VCC
WEN1
D1_15
D1_14
D1_13
D1_12
D1_11
D1_10
D1_9
D1_8
VCC
C101
0.1µF
U101
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
WEN
SEN
DNC
VCC
DNC
IW
GND
D17
VCC
D16
D15
D14
D13
GND
D12
D11
D10
D9
D8
VCC
C102
0.1µF
C103
0.1µF
Figure 5. PCB Schematic
Rev. 0 | Page 14 of 28
C104
0.1µF
C105
0.1µF
PC2
C106
0.1µF
R101
0Ω
CHANNEL B
IDT72V283
TOP FIFO
TQFP80
C107
0.1µF
R102
10kΩ
ALLOW Fx2 TO CONTROL FIFO’S OUTPUT WIDTH
C108
0.1µF
PC2: TRISTATED, NORMAL 16-BIT DATA PATH
PC2: DRIVEN HIGH, 9-BIT OUTPUT ALLOWS
READING 18 BITS IN TWO READS.
C109
0.1µF
GND
GND
GND
GND
VCC
VCC
VCC
Q17
Q16
Q15
Q14
Q13
Q12
Q10
Q11
OE
RT
Q9
Q8
Q7
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
OE1
Q17
Q16
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q7

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