COP8-EMFA-68P National Semiconductor, COP8-EMFA-68P Datasheet - Page 28

• Manufacturer Part Number: COP8-EMFA-68P
• Description: EMULATOR TARGET PACKAGE ADAPTER
• Manufacturer: National Semiconductor

Specifications of COP8-EMFA-68P

• Accessory Type: Emulator Target Package Adapter
• For Use With/related Products: Cop 8
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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6.0 Timers
6.2 TIMER T1 AND TIMER T2
The device has a set of two powerful timer/counter blocks,
T1, and T2. Since T1, and T2 are identical, except for the
high speed operation of T2, all comments are equally appli-
cable to either of the two timer blocks which will be referred
to as Tx. Differences between the timers will be specifically
noted.
Each timer block consists of a 16-bit timer, Tx, and two
supporting 16-bit autoreload/capture registers, RxA and
RxB. Each timer block has two pins associated with it, TxA
and TxB. The pin TxA supports I/O required by the timer
block, while the pin TxB is an input to the timer block. The
timer block has three operating modes: Processor Indepen-
dent PWM mode, External Event Counter mode, and Input
Capture mode.
The control bits TxC3, TxC2, and TxC1 allow selection of the
different modes of operation.
6.2.1 Timer Operating Speeds
T2 has the ability to operate at either the instruction cycle
frequency (low speed) or the internal clock frequency
(MCLK). For 10 MHz CKI, the instruction cycle frequency is
2 MHz and the internal clock frequency is 20 MHz. This
feature is controlled by the High Speed Timer Control Reg-
ister, HSTCR. Its format is shown below. To place a timer, Tx,
in high speed mode, set the appropriate TxHS bit to 1. For
low speed operation, clear the appropriate TxHS bit to 0.
This register is cleared to 00 on Reset.
6.2.2 Mode 1. Processor Independent PWM Mode
One of the timer’s operating modes is the Processor Inde-
pendent PWM mode. In this mode, the timers generate a
“Processor Independent” PWM signal because once the
timer is set up, no more action is required from the CPU
which translates to less software overhead and greater
throughput. The user software services the timer block only
when the PWM parameters require updating. This capability
is provided by the fact that the timer has two separate 16-bit
reload registers. One of the reload registers contains the
“ON” time while the other holds the “OFF” time. By contrast,
a microcontroller that has only a single reload register re-
quires an additional software to update the reload value
(alternate between the on-time/off-time).
The timer can generate the PWM output with the width and
duty cycle controlled by the values stored in the reload
registers. The reload registers control the countdown values
and the reload values are automatically written into the timer
when it counts down through 0, generating interrupt on each
reload. Under software control and with minimal overhead,
the PWM outputs are useful in controlling motors, triacs, the
intensity of displays, and in providing inputs for data acqui-
sition and sine wave generators.
In this mode, the timer Tx counts down at a fixed rate of t
(T2 may be selected to operate from MCLK). Upon every
underflow the timer is alternately reloaded with the contents
of supporting registers, RxA and RxB. The very first under-
flow of the timer causes the timer to reload from the register
Bit 7
0
Bit 6
0
Bit 5
0
(Continued)
Bit 4
0
HSTCR
Bit 3
0
Bit 2
0
Bit
1
0
T2HS
Bit
0
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RxA. Subsequent underflows cause the timer to be reloaded
from the registers alternately beginning with the register
RxB.
Figure 14 shows a block diagram of the timer in PWM mode.
The underflows can be programmed to toggle the TxA output
pin. The underflows can also be programmed to generate
interrupts.
Underflows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending flags under software control. Two control
enable flags, TxENA and TxENB, allow the interrupts from
the timer underflow to be enabled or disabled. Setting the
timer enable flag TxENA will cause an interrupt when a timer
underflow causes the RxA register to be reloaded into the
timer. Setting the timer enable flag TxENB will cause an
interrupt when a timer underflow causes the RxB register to
be reloaded into the timer. Resetting the timer enable flags
will disable the associated interrupts.
Either or both of the timer underflow interrupts may be
enabled. This gives the user the flexibility of interrupting
once per PWM period on either the rising or falling edge of
the PWM output. Alternatively, the user may choose to inter-
rupt on both edges of the PWM output.
6.2.3 Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that the
timer, Tx, is clocked by the input signal from the TxA pin after
synchronization to the appropriate internal clock (t
MCLK). The Tx timer control bits, TxC3, TxC2 and TxC1
allow the timer to be clocked either on a positive or negative
edge from the TxA pin. Underflows from the timer are latched
into the TxPNDA pending flag. Setting the TxENA control flag
will cause an interrupt when the timer underflows.
In this mode the input pin TxB can be used as an indepen-
dent positive edge sensitive interrupt input if the TxENB
control flag is set. The occurrence of a positive edge on the
TxB input pin is latched into the TxPNDB flag.
Figure 15 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the
TxA pin is being used as the counter input clock.
FIGURE 14. Timer in PWM Mode
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