Z8F64230100ZDF Zilog, Z8F64230100ZDF Datasheet - Page 211
![ADAPTER ICE Z8 ENCORE 64K 80QFP](/photos/9/2/90273/z8f64230100zdf_sml.jpg)
Z8F64230100ZDF
Manufacturer Part Number
Z8F64230100ZDF
Description
ADAPTER ICE Z8 ENCORE 64K 80QFP
Manufacturer
Zilog
Specifications of Z8F64230100ZDF
Module/board Type
*
For Use With/related Products
Z8 Encore!™
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3405
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PS019921-0308
START
DEBUG Mode
OCD Data Format
The operating characteristics of the Z8 Encore! XP
mode are:
•
•
•
•
•
Entering DEBUG Mode
The device enters DEBUG mode following any of the following operations:
•
•
•
Exiting DEBUG Mode
The device exits DEBUG mode following any of the following operations:
•
•
•
•
•
The OCD interface uses the asynchronous data format defined for RS-232. Each character
is transmitted as 1 Start bit, 8 data bits (least-significant bit first), and 1 Stop bit
(see
D0
The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to
execute specific instructions.
The system clock operates unless in STOP mode.
All enabled on-chip peripherals operate unless in STOP mode.
Automatically exits HALT mode.
Constantly refreshes the Watchdog Timer, if enabled.
Writing the DBGMODE bit in the OCD Control Register to 1 using the OCD interface.
eZ8 CPU execution of a BRK (Breakpoint) instruction (when enabled).
If the DBG pin is Low when the device exits Reset, the On-Chip Debugger
automatically puts the device into DEBUG mode.
Clearing the DBGMODE bit in the OCD Control Register to 0.
Power-On Reset
Voltage Brownout reset
Asserting the RESET pin Low to initiate a Reset.
Driving the DBG pin Low while the device is in STOP mode initiates a system reset.
Figure
D1
38).
Figure 38. OCD Data Format
D2
D3
D4
®
D5
F64XX Series devices in DEBUG
Z8 Encore! XP
D6
Product Specification
D7
®
On-Chip Debugger
F64XX Series
STOP
197
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