C8051T610DB32 Silicon Laboratories Inc, C8051T610DB32 Datasheet - Page 102

• Manufacturer Part Number: C8051T610DB32
• Description: DAUGHT BOARD T610 32TQFP SOCKET
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051T610DB32

• Module/board Type: Socket Module - TQFP
• Processor To Be Evaluated: C8051T61x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051T610DK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1505

C8051T610/1/2/3/4/5/6/7
19.2. Power-Fail Reset/V
When a power-down transition or power irregularity causes V
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 19.2). When V
to a level above V
memory contents are not altered by the power-fail reset, it is impossible to determine if V
the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V
monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other
reset source. For example, if the V
V
Important Note: If the V
is selected as a reset source. Selecting the V
lized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the V
state is shown below:
1. Enable the V
2. If necessary, wait for the V
3. Select the V
See Figure 19.2 for V
monitor reset. See Table 7.4 for complete electrical characteristics of the V
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monitor will still be disabled after the reset.
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RST
monitor as a reset source (PORSF bit in RSTSRC = 1).
monitor (VDMEN bit in VDM0CN = 1).
, the CIP-51 will be released from the reset state. Note that even though internal data
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monitor timing; note that the power-on-reset delay is not incurred after a V
monitor is being turned on from a disabled state, it should be enabled before it
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monitor to stabilize (see Table 7.4 for the V
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Monitor
monitor is disabled by code and a software reset is performed, the
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monitor and configuring it as a reset source from a disabled
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monitor as a reset source before it is enabled and stabi-
Rev 1.0
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to drop below V
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monitor.
Monitor turn-on time).
RST
, the power supply
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dropped below
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returns
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