V2DIP1-32 FTDI, Future Technology Devices International Ltd, V2DIP1-32 Datasheet - Page 11

• Manufacturer Part Number: V2DIP1-32
• Description: MOD MCU-USB HOST CTLR 24-DIP
• Manufacturer: FTDI, Future Technology Devices International Ltd
• Series: Vinculum-IIr

Specifications of V2DIP1-32

• Main Purpose: Interface, USB 2.0 Host/Controller
• Embedded: Yes, ASIC
• Utilized Ic / Part: VNC2-32Q
• Primary Attributes: Single A-Type Connector, UART / Parallel FIFO / SPI Interfaces
• Secondary Attributes: Second USB Port is Available via Pins, Traffic LEDs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 768-1058

3.6 Parallel FIFO Interface - Asynchronous Mode
The Parallel FIFO Asynchronous mode is functionally the same as the Parallel FIFO Interface available in
VNC1L VDIP1 module and has an eight bit data bus, individual read and write strobes and two hardware
flow control signals.
3.6.1 Signal Description - Parallel FIFO Interface
The Parallel FIFO Interface signals can be programmed to a choice of available I/O pins.
shows the Parallel FIFO Interface signals and the pins that they can be mapped.
J2-10, J1-6, J1-11
J2-9, J1-8, J1-12
J2-8, J1-9, J2-12
J2-6, J1-10, J2-11
J2-10, J1-6, J1-11
J2-9, J1-8, J1-12
J2-8, J1-9, J2-12
J2-6, J1-10, J2-11
J2-10, J1-6, J1-11
J2-9, J1-8, J1-12
J2-8, J1-9, J2-12
J2-6, J1-10, J2-11
Table 3.6 - Data and Control Bus Signal Mode Options – Parallel FIFO Interface
Available Pins
Copyright © 2010 Future Technology Devices International Limited
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fifo_data[0]
fifo_data[1]
fifo_data[2]
fifo_data[3]
fifo_data[4]
fifo_data[5]
fifo_data[6]
fifo_data[7]
fifo_txe#
fifo_rxf#
fifo_wr#
fifo_rd#
V2DIP1-32 VNC2-32Q Development Module Datasheet Version 1.01
Name
Output
Output
Type
Input
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
When high, do not read data from
the FIFO. When low, there is data
available in the FIFO which can be
read by strobing RD# low, then high.
When high, do not write data into the
FIFO. When low, data can be written
into the FIFO by strobing WR high,
then low.
Enables the current FIFO data byte
on D0...D7 when low. Fetches the
next FIFO data byte (if available)
from the receive FIFO buffer when
RD# goes from high to low
Writes the data byte on the D0...D7
pins into the transmit FIFO buffer
when WR goes from high to low.
Document Reference No.: FT_000163
FIFO data bus Bit 0
FIFO data bus Bit 1
FIFO data bus Bit 2
FIFO data bus Bit 3
FIFO data bus Bit 4
FIFO data bus Bit 5
FIFO data bus Bit 6
FIFO data bus Bit 7
Description
Clearance No.: FTDI# 150
Table 3.6
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