V2DIP1-64 FTDI, Future Technology Devices International Ltd, V2DIP1-64 Datasheet - Page 16
![MOD MCU-USB HOST CTLR 60-DIP](/photos/28/37/283703/v2dip1-64_sml.jpg)
V2DIP1-64
Manufacturer Part Number
V2DIP1-64
Description
MOD MCU-USB HOST CTLR 60-DIP
Manufacturer
FTDI, Future Technology Devices International Ltd
Series
Vinculum-IIr
Datasheet
1.V2DIP1-64.pdf
(26 pages)
Specifications of V2DIP1-64
Main Purpose
Interface, USB 2.0 Host/Controller
Embedded
Yes, ASIC
Utilized Ic / Part
VNC2-64Q
Primary Attributes
Single A-Type Connector, UART / Parallel FIFO / SPI Interfaces
Secondary Attributes
Second USB Port is Available via Pins, Traffic LEDs
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
768-1056
3.7 Parallel FIFO Interface-Synchronous Mode
The Parallel FIFO Synchronous mode has an eight bit data bus, individual read and write strobes, two
hardware flow control signals, an output enable and a clock out.
The synchronous FIFO mode uses the parallel FIFO interface signals detailed in Table 3.6 and additional
two signals detailed Table 3.8.
23, J1-3, J1-7, J2-8, J2-4
J2-17, J1-14, J1-18, J1-26, J1-30, J2-
27, J2-22, J1-4, J1-8, J2-7, J2-3
Table 3.8 - Data and Control Bus Signal Mode Options – Synchronous FIFO mode
3.7.1 Timing Diagram – Synchronous FIFO Mode Read and Write Cycle
When in Synchronous FIFO interface mode, the timing of a read and write operation on the FIFO interface
are shown in Figure 3.4 and Table 3.9
J2-14, J1-17, J1-24, J1-29, J2-28, J2-
Figure 3.4 - Synchronous FIFO Mode Read and Write Cycle
Available Pins
Copyright © 2010 Future Technology Devices International Limited
fifo_oe#
fifo_clkout
V2DIP1-64 VNCL2-64Q Development Module Datasheet Version 1.01
Name
Output
Output
Type
Document Reference No.: FT_000165
FIFO Output Enable
FIFO Output Enable
Description
Clearance No.: FTDI# 154
15