AD8321-EVAL Analog Devices Inc, AD8321-EVAL Datasheet

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AD8321-EVAL

Manufacturer Part Number
AD8321-EVAL
Description
BOARD EVAL FOR AD8321
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD8321-EVAL

Rohs Status
RoHS non-compliant
Main Purpose
Video, Video Processing
Utilized Ic / Part
AD8321
Secondary Attributes
-
Embedded
-
Primary Attributes
-
a
DESCRIPTION
The AD8321 is a low cost digitally controlled variable gain
amplifier optimized for coaxial line driving applications such as
cable modems that are designed to the DOCSIS* (upstream)
standard. An 8-bit serial word determines the desired output gain
over a 53.4 dB range, resulting in gain changes of 0.75 dB/LSB.
The AD8321 comprises a digitally controlled variable attenuator
of 0 dB to –53.4 dB, which is preceded by a low noise, fixed
gain buffer and followed by a low distortion high power ampli­
fier. The AD8321 accepts a differential or single-ended input
signal. The output is specified for driving a 75 W load, such as
coaxial cable, although the AD8321 is capable of driving other
loads. Performance of –53 dBc is achieved with an output level
up to 11 dBm at 42 MHz bandwidth using a 9 V supply.
A key performance and cost advantage of the AD8321 results
from the ability to maintain a constant 75 W output impedance
during power-up and power-down conditions. This eliminates
the need for external 75 W termination, resulting in twice the
effective output voltage when compared to a standard opera­
tional amplifier, thus eliminating the need for a transformer.
*Data-Over-Cable Service Interface Specifications
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
FEATURES
Linear in dB Gain Response Over >53 dB Range
Drives Low Distortion >11 dBm Signal into 75 � Load:
Very Low Output Noise Level
Maintains Constant 75 � Output Impedance
Upper Bandwidth: 235 MHz (Min Gain)
9 V Single Supply Operation
Power-Down Functionality
Supports SPI Interface
Low Cost
APPLICATIONS
Gain Programmable Line Driver
General Purpose IF Variable Gain Block
–53 dBc SFDR at 42 MHz
Power-Up and Power-Down Condition
No Line Transformer Required
HFC High Speed Data Modems
Interactive CATV Set-Top Boxes
CATV Plant Test Equipment
The AD8321 is packaged in a low cost 20-lead SOIC, operates
from a single +9 V supply, and has an operational temperature
range of –40∞C to +85∞C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/461-3113
VIN–
VIN+
DATEN CLK
–40
–50
–60
–70
–80
–90
Figure 1. Harmonic Distortion vs. Gain Control
0
INV
FUNCTIONAL BLOCK DIAGRAM
8
VCC
AD8321
16
© 2005 Analog Devices, Inc. All rights reserved.
Gain Programmable
GAIN CONTROL – Decimal
DATA SHIFT REGISTER
24
DATA SHIFT REGISTER
ATTENUATOR CORE
DATA LATCH
32
CATV Line Driver
SDATA
40
48
GND
f
V
(P
(P
MAX
O
IN
AD8321
IN
OUT
=
=
56
4
=
GAIN)
2MHz
137mV
–15dB
= 11d
POWER-
SWITCH
www.analog.com
DOWN/
INTER
REVERSE
AMP
64
Bm @
PWR
AMP
m)
p-p
HD3
HD2
72
VOUT
PD

Related parts for AD8321-EVAL

AD8321-EVAL Summary of contents

Page 1

... ATTENUATOR CORE VIN– DATA LATCH DATA SHIFT REGISTER DATA SHIFT REGISTER DATEN CLK SDATA The AD8321 is packaged in a low cost 20-lead SOIC, operates from a single +9 V supply, and has an operational temperature range of –40∞C to +85∞C. –40 –50 –60 –70 – ...

Page 2

... AD8321–SPECIFICATIONS Parameter INPUT CHARACTERISTICS Specified AC Voltage Noise Figure Input Resistance Input Capacitance GAIN CONTROL INTERFACE Gain Range Maximum Gain Minimum Gain Gain Scaling Factor OUTPUT CHARACTERISTICS Bandwidth (–3 dB) Bandwidth Roll-Off Bandwidth Peaking Output Offset Voltage Output Noise Spectral Density Output Noise Temperature Sensitivity 0 £ T ...

Page 3

... EH 8 CLOCK CYCLES GAIN TRANSFER (G1) T OFF T GS PEDESTAL Figure 2. Serial Interface Timing VALID DATA BIT MSB MSB CLK Figure 3. SDATA Timing –3– AD8321 Typ Max 5.0 0.8 20 –100 190 – ns MHz unless otherwise noted.) F CLK Typ Max 10 GAIN TRANSFER (G2 ...

Page 4

... AD8321ARZ –40∞C to +85∞C 2 AD8321ARZ-REEL –40∞C to +85∞C AD8321-EVAL 1 Thermal Resistance measured on SEMI standard 4-layer board Pb-free part. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. ...

Page 5

... OU T MAX GAIN) – FUNDAMENTAL FREQUENCY – MHz Figure 10. Third Order Harmonic Distortion vs. Frequency for Various Input Levels REV. A Typical Performance Characteristics–AD8321 30 20 71D 10 0 46D –10 23D –20 –30 00D –40 1000 0 100 FREQUENCY – MHz Figure 5. AC Response – ...

Page 6

... AD8321 34 MAX GAIN P = 11dBm OUT 10pF 0pF 20pF 50pF 100 FREQUENCY – MHz Figure 13. AC Response for Various Capacitor Loads 7.5mV V OUT p-p IN MAX GAIN tr(CLK) = 3ns CLK DATEN 5V 150ns Figure 16. Clock Feedthrough 1.5V MAX GAIN V OUT V IN 0.5V 30ns Figure 19. Overload Recovery ...

Page 7

... AD8321’s digital decode sec­ tion when the DATEN input is taken high. The gain of the AD8321 is linear in steps of 0.7526 dB. The gain transfer function starts at –27.43 dB (at decimal code 0) and increases 0.7526 dB/LSB. The gain increases up to decimal code 71 ...

Page 8

... As a result, the AD8321 line driver is required to vary its output applying attenuation or gain as needed so that all signals arriving at the central office are of the same amplitude. ...

Page 9

... Figure 25. If the BYP1 and/or BYP2 voltages are used externally, they should be buffered. External back termination resistors are not required when using the AD8321. The output impedance of the AD8321 and is maintained dynamically. This on chip back termination is maintained regardless of whether the amplifier is in forward transmit mode or reverse powered down mode ...

Page 10

... AD8321 Varying the Gain and SPI Programming The gain of the AD8321 can be varied over a range from approximately – +26 dB, in increments of approximately 0.7526 dB per LSB. Programming the gain of the AD8321 is accomplished using conventional Serial Peripheral Interface or SPI protocol. Three digital lines, DATEN, CLK and SDATA, are used to stream eight bits of data into the serial shift register of the AD8321 ...

Page 11

... AD8321 Variable Gain Upstream Power Amplifier via the parallel port of a PC. This evaluation package provides a convenient way to program the gain/attenuation of the AD8321 without the addition of any external glue logic. AD8321-EVAL has been developed to facilitate the use of the AD8321 in an application targeted at DOCSIS compliance. A low cost Alpha ...

Page 12

... Between Burst Transient Reduction for more specific details.) Enable Output Switch An Alpha Industries AS128-73 GaAs 2W Hi Linearity switch is installed on a standard AD8321-EVAL circuit and is controlled by the check box on the control panel portrayed in Figure 31. AD8321 This feature is intended to remove the output of the AD8321 from the VOUT port prior to using the “ ...

Page 13

... C6 0.1�F 10�F R8 1k� V1 P1–8 C16 1000pF R9 1k� V2 P1–7 C17 1000pF Figure 28. AD8321-EVAL Schematic of Single-Ended Inverting Input, Upstream PA Driver Solution Using AD8321, Matching Attenuator and Alpha Industries AS128-73 RF Switch REV. A C10 C12 1000pF 3 18 C11 4 17 AD8321 ...

Page 14

... AD8321 EVALUATION BOARD FEATURES AND OPERATION Figure 29. Evaluation Board Software Installation Figure 30. Evaluation Board Control Software –14– REV. A ...

Page 15

... Figure 31. Screen Display of Windows-Based Control Software REV. A –15– AD8321 ...

Page 16

... AD8321 Figure 32. Evaluation Board Silkscreen (Component Side) –16– REV. A ...

Page 17

... Figure 33. Evaluation Board Layout (Component Side) REV. A Figure 34. Evaluation Board Layout (Solder Side) –17– AD8321 ...

Page 18

... AD8321 AD8321 Evaluation Board Rev. B SINGLE- ENDED INVERTING INPUT March 17, 1999 Qty. Description 1350 size tantalum chip capacitor 2 0 1206 size ceramic chip capacitor 14 3 1,000 1206 size ceramic chip capacitor 82 1/8 W. 1206 size chip resistor 1/8 W. 1206 size chip resistor ...

Page 19

... Revision History Location 6/05—Data Sheet Changed from REV REV. A. Changes to ORDERING GUIDE ....................................................................................................................................................4 Updated OUTLINE DIMENSIONS.............................................................................................................................................19 REV. A OUTLINE DIMENSIONS 20-Lead Standard Small Outline Package [SOIC_W] Wide Body (R-20) Dimensions shown in millimeters and (inches) –19– AD8321 Page ...

Page 20

–20– ...

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