EVAL-ADE7763ZEB Analog Devices Inc, EVAL-ADE7763ZEB Datasheet - Page 46

• Manufacturer Part Number: EVAL-ADE7763ZEB
• Description: BOARD EVALUATION FOR ADE7763
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADE7763ZEB

• Main Purpose: Power Management, Energy/Power Meter
• Utilized Ic / Part: ADE7763
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

ADE7763
Serial Read Operation
During a data read operation from the ADE7763, data is shifted
out at the DOUT logic output upon the rising edge of SCLK. As
is the case with the data write operation, a write to the commu-
nication register must precede a data read.
With the ADE7763 in communication mode ( CS logic low),
first an 8-bit write to the communication register occurs. The
MSB of this byte transfer is a 0, indicating that the next data
transfer operation is a read. The LSBs of this byte contain the
address of the register that is to be read. The ADE7763 starts
shifting data out of the register upon the next rising edge of
SCLK—see
leaves its high impedance state and starts driving the data bus.
All remaining bits of register data are shifted out upon subsequent
SCLK rising edges. The serial interface also enters communica-
tion mode as soon as the read is complete. Then, the DOUT
SCLK
DOUT
DIN
CS
Figure 85
t
1
. At this point, the DOUT logic output
0
0
A5
COMMAND BYTE
A4
A3
A2
Figure 85. Serial Interface Read Timing
A1
A0
Rev. B | Page 46 of 56
t
t
9
11
DB7
logic output enters a high impedance state upon the falling edge
of the last SCLK pulse. The read operation can be aborted by
bringing the
complete. The DOUT output enters a high impedance state
upon the rising edge of CS .
When an ADE7763 register is addressed for a read operation,
the entire contents of that register are transferred to the serial
port. This allows the ADE7763 to modify its on-chip registers
without the risk of corrupting data during a multibyte transfer.
Note that when a read operation follows a write operation, the
read command (i.e., write to communication register) should
not happen for at least 4 μs after the end of the write operation.
If the read command is sent within 4 μs of the write operation,
the last byte of the write operation could be lost. This timing
constraint is given as timing specification t
MOST SIGNIFICANT BYTE
CS logic input high before the data transfer is
t
11
DB0
t
10
LEAST SIGNIFICANT BYTE
DB7
9
.
t
12
DB0
t
13