EVAL-AD74111EBZ Analog Devices Inc, EVAL-AD74111EBZ Datasheet - Page 4

• Manufacturer Part Number: EVAL-AD74111EBZ
• Description: BOARD EVAL FOR AD74111
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD74111EBZ

• Main Purpose: Interface, Analog Front End (AFE)
• Utilized Ic / Part: AD74111
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

AD74111
TIMING CHARACTERISTICS
Parameter
MASTER CLOCK AND RESET
SERIAL PORT
NOTES
1
2
3
4
Determines Master/Slave mode operation.
Applies in Slave mode only.
Applies in Master mode only.
Applies in Multiframe-Sync mode only.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MH
ML
RES
RS
RH
CH
CL
FD
FS
FH
DD
DS
DH
DT
MCLK High
MCLK Low
RESET Low
DIN Setup Time
DIN Setup Time
DCLK High
DCLK Low
DFS Delay
DFS Setup Time
DFS Hold Time
DOUT Delay
DIN Setup Time
DIN Hold Time
DOUT Three-State
RESET
MCLK
DIN
2
2
DCLK
DOUT
DFS
DIN
Figure 3. Load Circuit for Digital Output Timing Specifications
t
MH
(AVDD = 2.5 V ± 5%, DVDD2 = 2.5 V ± 5%, DVDD1 = 3.3 V ± 10%, f
T
A
t
ML
= T
TO OUTPUT
t
Figure 1. MCLK and RESET Timing
MIN
FD
Min
25
25
10
5
5
20
20
5
15
5
15
t
to T
FS
Figure 2. Serial Port Timing
PIN
t
MAX
FH
, unless otherwise noted.)
50pF
t
DD
C
Max
5
30
40
L
MSB
100 A
100 A
MSB
–4–
t
RES
t
CL
t
I
I
CH
OL
OH
MSB–1
Unit
ns
ns
ns
MCLKS
MCLKS
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RS
MSB–1
DVDD1
t
RH
2
t
DS
MSB–2
MSB–2
Comments
To RESET Rising Edge
To RESET Rising Edge
From DCLK Rising Edge
To DCLK Falling Edge
From DCLK Falling Edge
From DCLK Rising Edge
To DCLK Falling Edge
From DCLK Falling Edge
From DCLK Rising Edge
t
DH
MCLK
= 12.288 MHz, f
1
1
3
4
S
= 48 kHz,
REV. 0