CDB5460AU Cirrus Logic Inc, CDB5460AU Datasheet - Page 50

• Manufacturer Part Number: CDB5460AU
• Description: EVALUATION BOARD FOR CS5460A
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5460AU

• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CS5460A
• Primary Attributes: 1-Phase Current & Voltage Monitoring
• Secondary Attributes: Graphical User Interface, SPI™ & USB Interfaces
• Processor To Be Evaluated: CS5460A, C8051F320
• Interface Type: USB
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

5.12 Control Register
50
Res
CRDY
EDIR
EOUT
DRDY
Default** = 0x000000
STOP
MECH
INTL
SYNC
NOCPU
NOOSC
STEP
Res
Res
Res
23
15
7
Address: 28
MECH
Res
Res
which is usually 4 kHz.
ergy Accumulation Register (not accessible to user) to mandate the generation of one or more
pulses on the EOUT pin (if enabled, see Configuration Register). The energy flow may indicate
negative energy or positive energy. (The sign is determined by the EDIR bit, described above).
This EOUT bit is cleared automatically when the energy rate drops below the level that produc-
es a 4 kHz EOUT pin rate. The bit can also be cleared by writing to the Status Register. This
status bit is set with a maximum frequency of 4 kHz (when MCLK/K is 4.096 MHz). When
MCLK/K is not equal to 4.096 MHz, the user should scale the pulse-rate by a factor of
4.096 MHz / (MCLK/K) to get the actual pulse-rate.
data acquisition modes, this bit will indicate the end of computation cycles. When running cali-
brations, this bit indicates that the calibration sequence has completed, and the results have
been stored in the offset or gain registers.
22
14
Conversion Ready. Indicates a new conversion is ready. This will occur at the output word rate,
Data Ready. When running in ’single computation cycle’ or ’continuous computation cycles’
1 = used to terminate the new EEBOOT sequence.
Reserved. These bits must be set to zero.
1 = widens EOUT and EDIR pulses for mechanical counters.
1 = forces internal A/D converter clock to synchronize to the initiation of a conversion command.
1 = saves power by disabling the crystal oscillator for external drive.
Set whenever the EOUT bit asserted (see below) if the accumulated energy is negative.
Indicates that enough positive/negative energy has been reached within the internal EOUT En-
1 = converts the INT output to open drain configuration.
1 = converts the CPUCLK output to a one-bit output port. Reduces power consumption.
1 = enables stepper-motor signals on the EOUT/EDIR pins.
6
Res
Res
Res
21
13
5
INTL
Res
Res
20
12
4
SYNC
Res
Res
19
11
3
NOCPU
Res
Res
18
10
2
NOOSC
Res
Res
17
9
1
CS5460A
STOP
STEP
DS487F4
Res
16
8
0