EVAL-ADM1068LQEBZ Analog Devices Inc, EVAL-ADM1068LQEBZ Datasheet - Page 5

• Manufacturer Part Number: EVAL-ADM1068LQEBZ
• Description: BOARD EVALUATION FOR ADM1068LQ
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADM1068LQEBZ

• Main Purpose: Power Management, Power Supply Supervisor/Tracker/Sequencer
• Embedded: No
• Utilized Ic / Part: ADM1068
• Primary Attributes: 10 Channel Supervisor / Sequencer, 6 Voltage Output DACs
• Secondary Attributes: GUI Programmable via SMBus (via USB)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parameter
DIGITAL INPUTS (VXx, A0, A1)
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
SERIAL BUS TIMING
SEQUENCING ENGINE TIMING
1
2
Specification is not production tested but is supported by characterization data at initial product release.
At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.
Input High Voltage, V
Input Low Voltage, V
Input High Current, I
Input Low Current, I
Input Capacitance
Programmable Pull-Down Current,
Input High Voltage, V
Input Low Voltage, V
Output Low Voltage, V
Clock Frequency, f
Bus Free Time, t
Start Setup Time, t
Stop Setup Time, t
Start Hold Time, t
SCL Low Time, t
SCL High Time, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Data Setup Time, t
Data Hold Time, t
Input Low Current, I
State Change Time
Standard (Digital Output) Mode
Three-State Output Leakage Current
Oscillator Frequency
I
(PDO1 to PDO8)
V
V
I
I
R
I
PULL-DOWN
OL
SINK
SOURCE
OH
OL
PULL-UP
2
2
(VPx)
2
BUF
LOW
HIGH
HD;DAT
HD;STA
SCLK
SU;STA
SU;STO
SU;DAT
IL
IL
f
IL
IH
IL
r
IH
IH
OL
2
Min
2.4
V
0
16
90
2.0
−1
2.0
4.7
4.7
4
4
4.7
4
250
5
PU
− 0.3
Typ
20
100
5
20
10
Rev. B | Page 5 of 24
Max
4.5
0.50
20
60
29
2
10
110
0.8
1
0.8
0.4
400
1000
300
1
Unit
V
V
V
V
mA
mA
kΩ
mA
μA
kHz
V
V
μA
μA
pF
μA
V
V
V
kHz
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
μA
μs
Test Conditions/Comments
V
V
V
I
Maximum sink current per PDO pin
Maximum total sink for all PDO pins
Internal pull-up
Current load on any VPx pull-ups, that is, total source
current available through any number of PDO pull-up
switches configured onto any one VPx pin
V
All on-chip time delays derived from this clock
Maximum V
Maximum V
V
V
VDDCAP = 4.75 V, T
I
V
OL
OUT
PU
PU
PU
PDO
IN
IN
IN
= 20 mA
= 5.5 V
= 0 V
= 0 V
(pull-up to VDDCAP or VPx) = 2.7 V, I
to VPx = 6.0 V, I
≤ 2.7 V, I
= −3.0 mA
= 14.4 V
OH
IN
IN
= 5.5 V
= 5.5 V
= 0.5 mA
OH
A
= 25°C, if known logic state is required
= 0 mA
OH
= 0.5 mA
ADM1068