CRD42L52 Cirrus Logic Inc, CRD42L52 Datasheet - Page 30

• Manufacturer Part Number: CRD42L52
• Description: REFERENCE DESIGN FOR CS42L52
• Manufacturer: Cirrus Logic Inc

Specifications of CRD42L52

• Main Purpose: Audio, CODEC
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CS42L52
• Primary Attributes: 2 Stereo Analog Inputs, Stereo Line and Headphone Outputs, S/PDIF Transmitter and Receiver
• Secondary Attributes: Graphical User Interface
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1580

30
4.3.1
Referenced Control
PWM Control
SPKxMUTE .........................
MUTE50/50 .........................
SPKMONO ..........................
SPKxVOL[7:0] .....................
SPKSWAP...........................
SPKB=A ..............................
BATTCMP ...........................
VPREF[3:0] .........................
VPLVL[7:0] ..........................
PDN_SPKx[1:0]...................
SPKxSHRT..........................
Referenced Control
Analog Output
HPxMUTE ...........................
HPxVOL[7:0] .......................
PDN_HPx[1:0] .....................
HPGAIN[2:0]........................
PASSTHRUx .......................
PASSxMUTE .......................
PASSxVOL[7:0] ...................
CHGFREQ ..........................
from DSP
Engine
SPKAMUTE
SPKBMUTE
MUTE50/50
SPKMONO
SPKSWAP
SPKB=A
SPKAVOL[7:0]
SPKBVOL[7:0]
+0dB/-102dB
0.5dB steps
Beep Generator
The Beep Generator generates audio frequencies across approximately two octave major scales. It offers
three modes of operation: Continuous, multiple, and single (one-shot) beeps. Sixteen on and eight off
times are available.
Note:
iter function is used, it may be required to set the beep volume sufficiently below the threshold to prevent
the peak detect from triggering. Since the master volume control, MSTxVOL[7:0], will affect the beep vol-
ume, DAC volume may alternatively be controlled using the PMIXxVOL[6:0] bits.
Figure 11. PWM Output Stage
VOL
Compensation
The Beep is generated before the limiter and may affect desired limiting performance. If the lim-
Modulator
BATTCMP
VPREF[3:0]
VPLVL[7:0]
Battery
PDN_SPKA[1:0]
PDN_SPKB[1:0]
PWM
Register Location
“Speaker Mute” on page 54
“Speaker Mute 50/50 Control” on page 54
“Speaker MONO Control” on page 54
“Speaker Volume Control” on page 64
“Speaker Channel Swap” on page 54
“Speaker Volume Setting B=A” on page 54
“Battery Compensation” on page 71
“VP Reference” on page 72
“VP Voltage Level (Read Only)” on page 72
“Speaker Power Control” on page 44
“Speaker Current Load Status (Read Only)” on page 72
Register Location
“Headphone Mute” on page 54
“Headphone Volume Control” on page 63
“Headphone Power Control” on page 44
“Headphone Analog Gain” on page 51
“Passthrough Analog” on page 52
“Passthrough Mute” on page 52
“Passthrough x Volume” on page 57
“Charge Pump Frequency” on page 73
Gate
Drive
SPKASHRT
SPKBSHRT
Circuit
Short
Speaker
Outputs
+
+
-
-
A
B
5/13/08
from DSP
Engine
Analog Passthru
from PGA
Figure 12. Analog Output Stage
HPAMUTE
HPBMUTE
HPA_VOL[7:0]
HPB_VOL[7:0]
+0dB/-102dB
0.5dB steps
VOL
PASSAMUTE
PASSBMUTE
PASSAVOL[7:0]
PASSBVOL[70]
+12dB/-60dB
(uses PGA)
0.5dB steps
VOL
DAC
PASSTHRUA
PASSTHRUB
CHGFREQ[3:0]
PDN_HPA[1:0]
PDN_HPB[1:0]
Charge
Pump
HPGAIN[2:0]
CS42L52
DS680F1
HP/Line
Outputs
B
A