CDB42518 Cirrus Logic Inc, CDB42518 Datasheet - Page 5

• Manufacturer Part Number: CDB42518
• Description: BOARD EVAL FOR CS42518 CODEC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42518

• Main Purpose: Audio, CODEC
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: CS42518/16
• Primary Attributes: 6 Single-Ended Analog Inputs and 8 Outputs, S/PDIF Digital Audio Transmitter and Receiver
• Secondary Attributes: GUI, I2C, SPI Interfaces
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1502

The instrumentation amplifier is optionally inserted before the LPF by changing the FILT jumpers to position 2. The
instrumentation amplifier incorporates a 5x gain (+14dB) which effectively lowers the noise contribution of the fol-
lowing 2-pole LPF. This improves the overall dynamic range of the system. The gain of this stage is determined from
the following equation:
The resistor designated by R
feedback resistors on the two sides of the instrumentation amp ‘R’ must be equal.
A resistor divider pad (R66 and R84 for OUTA1) has been placed after the low pass filter to bring the circuit back to
unity gain (selectable with jumper J11 for OUTA1).
The attenuation provided by the output mute transistor (Q2 for OUTA1) is determined by the resistor-divider formed
between the collector-emitter on-resistance and the output resistor of the LPF (R66 for OUTA1). The greater the
output resistor, the greater the attenuation will be for a given transistor. The trade off is that a high output impedance
is not usually desirable, and may affect the voltage transfer to the next stage based upon its input impedance.
The same resistor that affects the transistor mute level also affects the HPF formed with the output DC-block capac-
itor (C63 for OUTA1). For LPF configuration 2, the values for the DC-block capacitor and output resistor pad (R66
and R84 for OUTA1) were chosen to give uniform distortion performance across the audio bandwidth, particularly
at low frequency. The HPF formed by this R-C pair must be such that the voltage across the aluminum electrolytic
DC-block capacitor must be a minimum at 20Hz. This keeps the distortion due to the electrolytic's dielectric absorp-
tion properties to a minimum. For a design utilizing only LPF configuration 1, there is no post-LPF resistor-divider
pad, and a much smaller value capacitor can be used.
1.7
The CPLD controls the on-board signal routing and configuration (see Figure 17). The CPLD interfaces with the
computer software through the DB-25 parallel port header, or can communicate with an external processor via the
External Control header.
1.8
On-board clock and data routing and configuration logic, as well as the CS42518 part are configured using a com-
puter with the supplied Windows-based software. The software communicates via the DB-25 parallel port interface
(see Figure 16) to a local CPLD that can configure all parts on the board.
1.9
A 26-pin dual-row header allows access to the control signals needed to configure the CS42518. The external con-
troller has access to the CS42518 I
able (see Figure 16). All control header signals are buffered, and are referenced to VLC levels. See Table 3 for a
complete description of External Control Header signals.
CPLD
DB-25 Computer Parallel Port
External Control Header
2
Figure 1. Instrumentation Amplifier Configuration
(see Figure 1) can be adjusted to change the gain of the instrumentation amp. The
2
C/SPI signals, master mute and reset, and the CS42518 interrupt signal is avail-
IN+
IN-
R2
Gain
=
R
R
1
+
2 R
------------
R 2
OUT+
OUT-
CDB42518
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