AD9859/PCB Analog Devices Inc, AD9859/PCB Datasheet - Page 17

• Manufacturer Part Number: AD9859/PCB
• Description: BOARD EVAL FOR AD9859
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9859/PCB

• Rohs Status: RoHS non-compliant
• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Embedded: No
• Utilized Ic / Part: AD9859
• Primary Attributes: 10-Bit DAC, 32-Bit Tuning Word Width
• Secondary Attributes: 400MHz, Graphical User Interface
• Lead Free Status / Rohs Status: Not Compliant

AUTO Shaped On-Off Keying Mode Operation
The auto-shaped on-off keying mode is active when CFR1<25>
and CFR1<24> are set. When auto-shaped on-off keying mode
is enabled, a single scale factor is internally generated and
applied to the multiplier input for scaling the output of the DDS
core block (see Figure 18). The scale factor is the output of a
10-bit counter that increments/decrements at a rate determined
by the contents of the 8-bit output ramp rate register. The scale
factor increases if the OSK pin is high and decreases if the OSK
pin is low. The scale factor is an unsigned value such that all 0s
multiply the DDS core output by 0 (decimal) and 0x3FFF multip-
lies the DDS core output by 16383 (decimal).
For users who use the full amplitude (10-bits) but need fast
ramp rates, the internally generated scale factor step size
is controlled via the ASF<15:14> bits. Table 6 describes the
increment/decrement step size of the internally generated scale
factor per the ASF<15:14> bits.
A special feature of this mode is that the maximum output
amplitude allowed is limited by the contents of the amplitude
scale factor register. This allows the user to ramp to a value less
than full scale.
Table 6. Auto-Scale Factor Internal Step Size
ASF<15:14> (Binary)
00
01
10
11
DDS CORE
AMPLITUDE SCALE
FACTOR REGISTER
COS(X)
Increment/Decrement Size
1
2
4
8
(ASF)
0
1
Figure 18. On-Off Shaped Keying, Block Diagram
0
OSK ENABLE
FACTOR GENERATOR
CFR<25>
OUT
OSK PIN
Rev. A | Page 17 of 24
INC/DEC ENABLE
AUTO SCALE
UP/DN
HOLD
TO DAC
SYNC_CLK
OSK Ramp Rate Timer
The OSK ramp rate timer is a loadable down-counter, which
generates the clock signal to the 10-bit counter that generates
the internal scale factor. The ramp rate timer is loaded with the
value of the ASFR every time the counter reaches 1 (decimal).
This load and countdown operation continues for as long as the
timer is enabled, unless the timer is forced to load before
reaching a count of 1.
If the load OSK timer bit (CFR1<26>) is set, the ramp rate
timer is loaded upon an I/O UPDATE or upon reaching a value
of 1. The ramp timer can be loaded before reaching a count of 1
by three methods.
Method one is by changing the OSK input pin. When the OSK
input pin changes state, the ASFR value is loaded into the ramp
rate timer, which then proceeds to count down as normal.
The second method in which the sweep ramp rate timer can be
loaded before reaching a count of 1 is if the load OSK timer bit
(CFR1<26>) is set and an I/O UPDATE is issued.
The last method in which the sweep ramp rate timer can be
loaded before reaching a count of 1 is when going from the
inactive auto-shaped on-off keying mode to the active auto-
shaped on-off keying mode; that is, when the sweep enable bit is
being set.
AUTO DESK
CFR1<24>
ENABLE
RAMP RATE TIMER
LOAD OSK TIMER
CFR1<26>
AMPLITUDE RAMP
RATE REGISTER
LOAD
(ASF)
DATA
EN
CLOCK
AD9859