AD9858/TLPCBZ Analog Devices Inc, AD9858/TLPCBZ Datasheet - Page 22

• Manufacturer Part Number: AD9858/TLPCBZ
• Description: BOARD EVAL TRANSLATION LOOP
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9858/TLPCBZ

• Design Resources: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Utilized Ic / Part: AD9858/TL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

AD9858
REGISTER MAP
The registers are listed in Table 6. The serial address and parallel address numbers associated with each of the registers are shown in
hexadecimal format. Square brackets [] are used to reference specific bits or ranges of bits. For example, [3] designates Bit 3, and [7:3]
designates the range of bits from 7 down to 3, inclusive.
Table 6.
Register
Name
Control
function
register
(CFR)
Delta freq.
tuning
word
(DFTW)
Delta
frequency
ramp rate
(DFRRW)
Frequency
Tuning
Word 0
(FTW0)
Phase
Offset
Word 0
(POW0)
Frequency
Tuning
Word 1
(FTW1)
Phase
Offset
Word 1
(POW1)
Frequency
Tuning
Word 2
(FTW2)
Ser
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Address
Par
0x00
[7:0]
0x01
[15:8]
0x02
[23:16]
0x03
[31:24]
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
(MSB)
Bit 7
Not
used
Freq.
sweep
enable
Auto Clr
freq.
accum
Frequency detect
pump current
mode charge
(see Table 7)
Not used
Not used
Bit 6
2 GHz
divider
disable
Enable
sine
output
Auto Clr
phase
accum
Bit 5
SYNCLK
disable
Charge
pump
offset
Load
delta
freq
timer
mode charge pump current
Delta Frequency Ramp Rate Word[15:8]
Delta Frequency Ramp Rate Word[7:0]
Frequency Tuning Word 0[23:16]
Frequency Tuning Word 0[31:24]
Frequency Tuning Word 1[23:16]
Frequency Tuning Word 1[31:24]
Frequency Tuning Word 2[23:16]
Frequency Tuning Word 2[31:24]
Frequency Tuning Word 0[15:8]
Frequency Tuning Word 1[15:8]
Frequency Tuning Word 2[15:8]
Final closed-loop
Frequency Tuning Word 0[7:0]
Frequency Tuning Word 1[7:0]
Frequency Tuning Word 2[7:0]
Delta Frequency Word[23:16]
Delta Frequency Word[31:24]
Rev. C | Page 22 of 32
Delta Frequency Word[15:8]
Delta Frequency Word[7:0]
(see Table 8)
Phase Offset Word 0[7:0]
Phase Offset Word 1[7:0]
Bit 4
Mixer
power-
down
Phase detector
divider ratio (N)
(see Table 10)
Clear
freq
accum
Phase Offset Word 0[13:8]
Phase Offset Word 1[13:8]
Bit 3
Phase
detect
power-
down
Clear
phase
accum
Bit 2
Power-
down
Charge
pump
polarity
Not
used
Wide closed-loop mode
charge pump current
(see Table 9)
Bit 1
SDIO
input
only
Phase detector
divider ratio (M)
(see Table 11)
Fast
lock
enable
(LSB)
Bit 0
LSB first
FTW for
fast lock
Default
Value
0x18
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Profile
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
0
0
0
0
0
1
1
1
1
1
1
2
2
2
2