ADV212-HD-EB Analog Devices Inc, ADV212-HD-EB Datasheet - Page 39

BOARD EVALUATION FOR ADV212-HD

ADV212-HD-EB

Manufacturer Part Number
ADV212-HD-EB
Description
BOARD EVALUATION FOR ADV212-HD
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADV212-HD-EB

Main Purpose
Video, Video Processing
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
ADV212-HD
Primary Attributes
1080i and 720p SDI Compatible, 32/64-bit, 33/66 MHz PCI Card
Secondary Attributes
GUI, JPEG2000 Video Codec
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
HIPI (HOST INTERFACE—PIXEL INTERFACE)
Figure 38 is a typical configuration using HIPI mode.
32-BIT HOST
DATA<31:0>
DREQ
DACK
DREQ
DACK
ACK
IRQ
WR
CS
RD
Figure 38. Host Interface—Pixel Interface Mode
Y0/G0<MSB>
Y0/G0<6>
Y0/G0<5>
Y0/G0<4>
Y0/G0<3>
Y0/G0<2>
Y0/G0<1>
Y0/G0<0>
Cb0/G1<MSB>
Cb0/G1<6>
Cb0/G1<5>
Cb0/G1<4>
Cb0/G1<3>
Cb0/G1<2>
Cb0/G1<1>
Cb0/G1<0>
Y1/G2<MSB>
Y1/G2<6>
Y1/G2<5>
Y1/G2<4>
Y1/G2<3>
Y1/G2<2>
Y1/G2<1>
Y1/G2<0>
Cr0/G3<MSB>
Cr0/G3<6>
Cr0/G3<5>
Cr0/G3<4>
Cr0/G3<3>
Cr0/G3<2>
Cr0/G3<1>
Cr0/G3<0>
74.25MHz
Rev. B | Page 39 of 44
HDATA<31>
HDATA<30>
HDATA<29>
HDATA<28>
HDATA<27>
HDATA<26>
HDATA<25>
HDATA<24>
HDATA<23>
HDATA<22>
HDATA<21>
HDATA<20>
HDATA<19>
HDATA<18>
HDATA<17>
HDATA<16>
HDATA<15>
HDATA<14>
HDATA<13>
HDATA<12>
HDATA<11>
HDATA<10>
HDATA<9>
HDATA<8>
HDATA<7>
HDATA<6>
HDATA<5>
HDATA<4>
HDATA<3>
HDATA<2>
HDATA<1>
HDATA<0>
CS
RD
WE
ACK
IRQ
DREQ0
DACK0
DREQ1
DACK1
MCLK
ADV212
COMPRESSED
DATA PATH
RAW PIXEL
DATA PATH
ADV212

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