ISD-ES511 Nuvoton Technology Corporation of America, ISD-ES511 Datasheet
ISD-ES511
Specifications of ISD-ES511
Related parts for ISD-ES511
ISD-ES511 Summary of contents
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... ISD5100 SERIES SINGLE-CHIP MINUTES DURATION VOICE RECORD/PLAYBACK DEVICES WITH DIGITAL STORAGE CAPABILITY ISD5100 SERIES Publication Release Date: Oct 31, 2008 - 1 - Revision 1.42 ...
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... Memo and Call Playback ..................................................................................................26 6.3.11 Message Cueing...............................................................................................................27 6.4. Analog Mode ............................................................................................................................28 6.4.1 Aux In and Ana In Description ..........................................................................................28 6.4.2 ISD5100 Series Analog Structure (left half) Description ..................................................29 6.4.3 ISD5100 Series Aanalog Structure (right half) Description ..............................................30 6.4.4 Volume Control Description..............................................................................................31 6.4.5 Speaker and Aux Out Description ....................................................................................32 6.4.6 Ana Out Description ...
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... Plastic Small Outline Integrated Circuit (SOIC)............................................78 11.4. 28-Lead 600-Mil Plastic Dual Inline Package (PDIP) ..............................................................79 11.5. ISD5116 Die Information..........................................................................................................80 11.6. ISD5108 Die Information..........................................................................................................82 11.7. ISD5104 Die Information..........................................................................................................84 11.8. ISD5102 Die Information..........................................................................................................86 12. ORDERING INFORMATION ...........................................................................................................88 13. VERSION HISTORY........................................................................................................................ Serial Interface...............................................................................70 ...
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... ISD5102 from minutes Analog functions and audio gating have also been integrated into the ISD5100 Series products to allow easy interface with integrated digital cellular chip sets on the market. Audio paths have been designed to enable full duplex conversation record, voice memo, answering machine (including outgoing message playback) and call screening features ...
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... Dual storage of digital and analog data • Durations Device ISD5102 Duration minutes Low Power Consumption • Supply Voltage Commercial Temperature = +2.7V to +3.3V Industrial Temperature = +2.7V to +3.3V (+2.7V to +3.6V for ISD5108 only) • Supports 2.0V and 3.0V interface logic • Operating Current (typical) CC Play (typical) CC Rec ...
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... BLOCK DIAGRAM ISD5100-Series Block Diagram 6dB MICROPHONE MIC+ MIC IN AGC MIC - 1 (AGPD) AGCCAP AUX IN FILTO ANA IN 1 (INS0) AUX IN AUX IN ARRAY AMP 1 (AXPD) ( AXG0 ) 2 AXG1 XCLK ANA IN ANA IN AMP 1 (AIPD AIG0 ) AIG1 Power Conditioning CCA SSA SSA SSD SSD SUM1 Summing ...
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... NC 21 MIC AUX OUT V SSA 19 AUX IN MIC- 18 ANA IN ANA OUT ANA OUT- CCA 16 SP+ ACAP 15 V SP- SSA ISD5116 6 7 ISD5108 8 ISD5104 9 ISD5102 TSOP - 7 - ISD5100 SERIES CCD CCD 26 3 XCLK 25 INT RAC SSA ISD5116 AUX OUT 19 10 AUX ANA CCA 16 13 SP+ ...
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... This pin must be grounded for utilizing internal clock. For precision timing control, external clock signal can be applied through this pin. Digital Supply Voltage. These pins supply power to the digital sections of the device. They must be carefully bypassed to Digital Ground to insure correct device operation ISD5100 SERIES 2 C interface Slave Address Slave Address ...
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... In addition, the device can be re-recorded over 10,000 times (typically) for the digital data and over 100,000 times (typically) for the analog messages. A new feature has been added that allows memory space in the ISD5100 Series to be allocated to either digital or analog storage when recorded. The fact that a section has been assigned digital or analog data is stored in the Message Address Table by the system microcontroller when the recording is made ...
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... UNCTIONAL ETAILS The ISD5100 Series are single chip solutions for analog and digital data storage. The array can be divided between analog and digital storage according to user’s choice, when the device is configured. The below block diagram shows that the ISD5116 device can be easily designed into a telephone answering machine (TAD) ...
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... Using this table allows efficient message management. Segments of messages can be stored wherever there is available space in the memory array. [This is explained in detail for the ISD5008 in Applications Note #9 and will be similarly described in a later Note for the ISD5100-Series.] ...
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... I C Slave Address The ISD5100 Series have 7-bit slave address of <100 00xy> where x and y are equal to the state, respectively, of the external address pins A1 and A0. Because all data bytes are required bits, the LSB of the address byte is the Read/Write selection bit that tells the slave whether to transmit or receive data ...
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... There are many control functions used to operate the ISD5100-Series. Among them are: 6.3.1.1. Read Status Command: The Read Status command is a read request from the Host processor to the ISD5100 Series without delivering a Command Byte. The Host supplies all the clocks (SCL). In each case, the entity sending the data drives the data line (SDA) ...
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... See the caption box above for more explanation. S SLAVE ADDRESS 2 C STOP DATA SLAVE ADDRESS R A DATA A DATA High Addr. Status - 14 - ISD5100 SERIES 2 Conventions used Data Transfer Diagrams S = START Condition = STOP Condition P = 8-bit data transfer R = “1” in the R/W bit = “0” in the R/W bit ACK (Acknowledge) ...
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... Slave responds with an ACK 13. Wait for SCL to go HIGH 2 14. Host executes I C STOP S SLAVE ADDRESS S SLAVE ADDRESS W A DATA A DATA Command High Addr ISD5100 SERIES W A DATA A Command Byte A DATA A P Low Addr. Publication Release Date: Oct 31, 2008 Revision 1.42 P ...
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... Command Byte Control of the ISD5100 Series are implemented through an 8-bit command byte, sent after the 7-bit device address and the 1-bit Read/Write selection bit. The 8 bits are: Global power up bit ...
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... Write: digital write command Erase: digital page and block erase command Power up: global power up/down bit. (C7) Load CFG0: load configuration register 0 Load CFG1: load configuration register 1 Read STATUS: Read the interrupt status and address register, including a hardwired device ID ISD5100 SERIES RG2 RG1 ...
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... DIGITAL WRITE @ ADDR DIGITAL READ DIGITAL READ @ ADDR 1 READ STATUS 1. See section 7.2 on page 12 for details. Pwr Function Bits HEX PU DAB FN2 FN1 CMD N/A N/A N/A N/A Publication Release Date: Oct 31, 2008 - 18 - ISD5100 SERIES Register Bits FN0 RG2 RG1 RG0 ...
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... Depending upon the design and the number of pins available on the controller, the polling overhead can be reduced. If INT and RAC are tied to the microcontroller, it does not have to poll as frequently to determine the status of the ISD5100-SERIES. Indicates whether an EOM interrupt has occurred. ...
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... Configuration Register Bytes The configuration register bytes are defined, in detail, in the drawings of drawings display how each bit enables or disables a function of the audio paths in the ISD5100- Series. The tables below give a general illustration of the bits. There are two configuration registers, CFG0 and CFG1, so there are four 8-bit bytes to be loaded during the set-up of the device. ...
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... VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD VLS1 VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD 6.3.6 Power-up Sequence This sequence prepares the ISD5100 Series for an operation to follow, waiting the Tpud time before sending the next command sequence ...
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... Chip Set ANA IN The figure above shows the part of the ISD5100 Series block diagram that is used in Feed Through Mode. The rest of the chip will be powered down to conserve power. The bold lines highlight the audio paths. Note that the Microphone to ANA OUT +/– path is differential. ...
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... AUX output stage. The status of the rest of the functions in the ISD5100 Series chip must be defined before the con- figuration registers settings are updated: 1. Power down the Volume Control Element — Bit VLPD controls the power up state of the Volume Control ...
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... The call record mode adds the ability to record an incoming phone call. In most applications, the ISD5100 Series would first be set up for Feed Through Mode as described above. When the user wishes to record the incoming call, the setup of the chip is modified to add that ability. For the purpose of this explanation, we will use the 6 ...
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... SUM1 SUMMING amplifier. These are bits D7 and D8 respectively of CFG1 and they should be set to the state where D7 is ZERO and D8 is ONE to select the INPUT SOURCE MUX (only) path. ISD5100 SERIES Publication Release Date: Oct 31, 2008 - 25 - Revision 1.42 ...
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... S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6 respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW PASS FILTER (only) path. ISD5100 SERIES Publication Release Date: Oct 31, 2008 - 26 - Revision 1.42 ...
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... This operation is used during playback. In this mode, the messages are skipped 512 times faster than in normal playback mode. It will stop when an EOM marker is reached. Then, the internal address counter will be pointing to the next message. ISD5100 SERIES Publication Release Date: Oct 31, 2008 - 27 - ...
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... ODE 6.4.1 Aux In and Ana In Description The AUX additional audio input to the ISD5100-Series, such as from the microphone circuit in a mobile phone “car kit.” This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB). See the AUX IN Amplifier Gain Settings table ...
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... ISD5100 Series Analog Structure (left half) Description INP INPU RCE MUX AGC AMP AMP (INS0) S UM1 MUX AMP INSO Source 2 (S1S1,S1S0) 0 AGC AMP 1 AUX IN AMP AIG1 AIG0 AIPD AXG1 AXG0 AXPD INS0 VLS0 VOL2 VOL 1 VOL0 S1S1 UMMING AMP Σ ...
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... ISD5100 Series Aanalog Structure (right half) Description FILTER MUX MUX SUM1 ARR AY FLS0 SOURCE 0 SUM1 1 ARRAY FLPD CONDITION 0 Power Up 1 Power Down ANA IN AMP XCL K FLD1 FLD0 SAMPLE FILTER RATE BANDWIDTH KHz 3.6 KHz 0 1 6.4 KHz 2.9 KHz 1 0 5.3 KHz 2 ...
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... VOL AMP MUX S UM2 S UM1 INP 2 (VLS1,VLS0) VLS1 VLS0 SOURCE 0 0 ANA IN AMP 0 1 SUM2 1 0 SUM1 1 1 INP AIG1 AIG0 AIPD AXG1 AXG0 AXPD VOL VOL 2 VOL1 ISD5100 SERIES VOLU CONT ROL 3 1 (VLPD) (VOL2,VOL1,VOL0) VOL2 VOL1 VOL INS0 AOS 2 ...
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... VOL 1 1 ANA FILTO 1 SUM2 AOS 2 AOS1 AOS0 AOPD OPS1 OPS 0 OPA1 OPA ISD5100 SERIES Car eaker AUX OUT 0 Power Down Power Down 1 @ 150 Ω Power Down 3.6 V P-P 0 23.5 mWatt @ 8 Ω Power Down 1 Power Down 1 V Max @ 5 KΩ P-P 1 ...
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... N N INS 0 A OS2 AOS1 AOS0 A OPD OPS1 - 33 - ISD5100 SERIES ( from AY) (69 4 mVp fro m mi crop ho ne inp ut) Chip Set A NA OUT OUT– AOPD CONDITION 0 Power Up 1 Power Down CFG0 OPS0 OPA1 OPA0 VL PD Publication Release Date: Oct 31, 2008 ...
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... ANA IN 11 Input Amplifier Note: Ra & Rb are in k Ω COUP ANA IN Amplifier Gain Settings CFG0 AIG1 AIG0 ISD5100 SERIES AGPD CONDITION 0 Power Up 1 Power Down 1 0 CFG1 GPD Resistor Ratio Gain (Rb/Ra) 63.9 / 102 0.625 77.9 / 88.1 0.883 92.3 / 73.8 1.250 106 / 60 1 ...
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... Speaker Out gain set to 1.6 (High). (Differential) AUX IN (Auxiliary Input) The AUX additional audio input to the ISD5100-Series, such as from the microphone circuit in a mobile phone “car kit.” This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB). See the following table. Additional gain is available steps (controlled by the ...
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... If an active command is sent before the internal cycle is finished, the part will hold SCL LOW until the current command is finished. After writing is complete, send the EXIT DIGITAL MODE command. ISD5100 SERIES 2 C acknowledge generated by the chip. Data for each block ...
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... Then the data direction is reversed by sending a repeated start condition, and the slave address with R/W set to 1. After this, the slave device (ISD5100- Series) begins to send data to the master until the master generates a NACK. If the part encounters ...
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... Write, Slave address zero WaitACK WaitSCLHigh SendByte(0xc0) - Stop digital erase WaitACK WaitSCLHigh I2CStop wait until erase of the last row has completed { wait RAC low WAIT RAC high } I2CStart SendByte(0x80) - Write, Slave address zero ISD5100 SERIES Publication Release Date: Oct 31, 2008 - 38 - Revision 1.42 ...
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... When the erase of the last desired row begins, the following STOP command (Command Byte = 80 hex) must be issued. This command must be completely given, including receiving the ACK from the Slave before the RAC pin goes HIGH at the end of the row. ISD5100 SERIES Publication Release Date: Oct 31, 2008 - 39 - Digital Erase Revision 1 ...
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... Last erased row Note Note S SLAVE ADDRESS W A CON A Erase starts on falling edge of Slave acknowledge D1 A DATA A DATA A High Addr. Byte Low Addr. Byte S SLAVE ADDRESS 40h Publication Release Date: Oct 31, 2008 - 40 - ISD5100 SERIES P P Note Command Byte A P Revision 1.42 ...
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... AUTOMATICALLY 6/20/2002 BOJ Revision B TO ERASE MULTIPLE (n) PAGES NO NO RAC\ ~ 125 uS STOP COMMAND MUST BE FINISHED BEFORE RAC\ RISES RAC\ SIGNAL 250 uS 1. ISD5100 SERIES (ROWS) COUNT RAC RAC\ ~ 250 uS FOR n-1 YES SEND STOP COMMAND 80,C0 BEFORE NEXT RAC NO WAIT FOR ...
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... WaitSCLHigh SendByte(0xc9) - Write Digital Data Command WaitACK WaitSCLHigh SendByte(row/256) - high address byte WaitACK WaitSCLHigh SendByte(row%256) - low address byte WaitACK WaitSCLHigh repeat until all data is sent { SendByte(data) - send data byte WaitACK() WaitSCLHigh() } I2CStop ISD5100 SERIES Publication Release Date: Oct 31, 2008 - 42 - Revision 1.42 ...
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... Exit Digital Mode Command WaitACK WaitSCLHigh I2CStop S SLAVE ADDRESS S SLAVE ADDRESS S SLAVE ADDRESS W A CON W A C9h A DATA Command Byte High Addr. Byte DATA A DATA W A 40h - 43 - ISD5100 SERIES DATA A Low Addr. Byte A DATA Publication Release Date: Oct 31, 2008 Revision 1.42 ...
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... rie ita rite D ig ita ita vis ISD5100 SERIES N O Publication Release Date: Oct 31, 2008 Revision 1.42 ...
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... Send repeat start command SendByte(0x81) - Read, Slave address zero repeat until all data is read { data = ReadByte() - send clocks to read data byte SendACK - send NACK on the last byte WaitSCLHigh - The only flow control available ISD5100 SERIES Publication Release Date: Oct 31, 2008 - 45 - Revision 1.42 ...
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... WaitACK WaitSCLHigh I2CStop S SLAVE ADDRESS W S SLAVE ADDRESS Command Byte S SLAVE ADDRESS S SLAVE ADDRESS W A CON A E1h A DATA High Addr. Byte R A DATA A DATA ISD5100 SERIES DATA A Low Addr. Byte A DATA N P 40h A P Publication Release Date: Oct 31, 2008 Revision 1.42 ...
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... rie ita ita ita vis ISD5100 SERIES N O Publication Release Date: Oct 31, 2008 Revision 1.42 ...
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... RAC stays HIGH for 248 ms and stays LOW for the remaining 8 ms before it reaches the end of a row. There are 2048 rows of memory in the ISD5116 devices, 1024 rows in the ISD5108, 512 rows in the ISD5104 and 256 rows in the ISD5102. ...
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... RAC Waveform During Digital Erase @ 8kHz Operation INT (Interrupt) INT is an open drain output pin. The ISD5100 Series interrupt pin goes LOW and stays LOW when an Overflow (OVF) or End of Message (EOM) marker is detected. Each operation that ends in an EOM or OVF generates an interrupt, including the message cueing cycles. The interrupt is cleared by a READ STATUS instruction that will give a status byte out the SDA line ...
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... A0, A1 (Address Pins) These two pins are normally strapped for the desired address that the ISD5100 Series will have on the serial interface. If there are four of these devices on the bus, then each must be strapped differently in order to allow the Master device to address them individually. The possible addresses range from 80h to 87h, depending upon whether the device is being written to, or read from, by the host ...
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... O PA0) OPA1 AOS2 A OS1 AOS0 AOPD OPS1 OPS0 OPA 1 OPA0 Publication Release Date: Oct 31, 2008 - 51 - ISD5100 SERIES Car Kit ( Max) Speaker OPA0 SPKR DRIVE AUX OUT 0 Power Down Power Down 1 3.6 V @150 Power Down Ω p.p 0 23.5 mWatt @ 8 Power Down Ω ...
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... ANA IN Input Amplifier 11 Note: Ra & Rb are in k Ω CCUP ANA IN Amplifier Gain Settings CFG0 AIG1 AIG0 ISD5100 SERIES Resistor Gain Gain Ration (Rb/Ra) 63.9 / 102 0.625 77.9 / 88.1 0.88 92.3 / 73.8 1.25 106 / 60 1.77 (2) Gain Array Speaker In/Out V Out V P-P 0.625 ...
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... AUX IN (Auxiliary Input) The AUX additional audio input to the ISD5100-Series, such as from the microphone circuit in a mobile phone “car kit.” This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB). See the AUX IN Amplifier Gain Settings table 2 steps (controlled by the I C interface ...
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... Power and Ground Pins (Voltage Inputs) CCA CCD To minimize noise, the analog and digital circuits in the ISD5100 Series devices use separate power busses. These +3 V busses lead to separate pins. Tie the V decouple both supplies as near to the package as possible (Ground Inputs) SSA SSD The ISD5100 Series utilizes separate analog and digital ground busses ...
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... Note XCLK C1=C2=C3=0.1 uF chip Capacitors Note 3 Analog Ground V SSA V CCD V CCD V SSD V SSD supply feedpoint. SS supply feedpoint. CC CCA Publication Release Date: Oct 31, 2008 - 55 - ISD5100 SERIES CCA V SSA V SSA and V supplies will also need filter CCD Revision 1.42 V CCA V SSA ...
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... ISD5100 SERIES Publication Release Date: Oct 31, 2008 - 56 - Revision 1.42 ...
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... TIMING DIAGRAMS 2 7 IMING IAGRAM START SDA SCL SU-DAT t HIGH t LOW t SCLK - 57 - ISD5100 SERIES STOP SU-STO Publication Release Date: Oct 31, 2008 Revision 1.42 ...
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... HIGH t 4.7 - SU-STA t 250 - SU-DAT t - 1000 300 f t 4.0 - SU-STO t 4.7 - BUF C - 400 ISD5100 SERIES FAST-MODE MIN. MAX. 0 400 0.6 - 1.3 - 0.6 - 0.6 - (1) 100 - ( 0.1C 300 b ( 0.1C 300 b 0 400 0 0 C-interface system, but the 2 C -interface specification) Publication Release Date: Oct 31, 2008 Revision 1 ...
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... LAYBACK AND TOP YCLE t START SDA PLAY AT ADDR SCL DATA CLOCK PULSES ANA IN ANA OUT ISD5100 SERIES t STOP STOP STOP Publication Release Date: Oct 31, 2008 - 59 - Revision 1.42 ...
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... XAMPLE OF OWER OMMAND FIRST BITS - 60 - ISD5100 SERIES Publication Release Date: Oct 31, 2008 Revision 1.42 ...
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... Junction temperature Storage temperature range Voltage Applied to any pads Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability. Functional operation is not implied at these conditions. Condition - 61 - ISD5100 SERIES (1) Value 0 150 - +150 0.3V ...
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... Voltage Applied to any pins OPERATING CONDITIONS (DIE) Conditions Die operating temperature range [2] Supply voltage ( [3] Ground voltage ( Voltage Applied to any pads [1] [2] Case temperature [1] [1] ISD5102, ISD5104, ISD5116 ISD5108 [1] [ CCA CCD SS Publication Release Date: Oct 31, 2008 - 62 - ISD5100 SERIES Values 0 ° +70 ° C +2.7V to +3.3V ...
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... All min/max limits are guaranteed by Nuvoton via electrical testing or characterization. Not all specifications are 100 percent tested. [3] All V and V are connected appropriately and others are floated (2) (1) Min Typ 0.8 CC Low for 2V 1.6 V – 0 ISD5100 SERIES (2) Max Unit Conditions µA OL 0.4 V Apply only SCL, SDA V Apply only SCL, SDA 0 ...
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... ISD5108 ISD5104 8.73 4.36 2.18 5.45 10.9 2.72 6.55 13.1 3.27 8.75 17.5 4. 256 320 384 - 64 - ISD5100 SERIES (2) Max Units Conditions kHz (5) kHz (5) kHz (5) kHz (5) kHz Knee Point kHz Knee Point kHz Knee Point kHz Knee Point ISD5102 min (6) 1.08 min (6) 1 ...
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... RAC Clock Low Time in RACEL Digital Erase mode 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) THD Total Harmonic Distortion ANA IN to ARRAY, ARRAY to SPKR ISD5100 SERIES 512 8 10 12.1 16 500 625 750 1000 15.6 19 ...
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... ANA IN Input Resistance (6 ANA +15 dB) (2) (1)(14) Min Typ reference 208 level point 5.5 6.0 +/-0 (2) (1)(14) Min Typ Input 1 + -0.5 +/-0 100 - 66 - ISD5100 SERIES (2) Max Units Conditions (4)(8) 300 mV Peak-to-Peak (4)(10) mV Peak-to-Peak 6 kHz at (4) (0TLP kHz –40 dB 0TLP Input MIC- and MIC+ kΩ pins 40 ...
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... Input 694 -0.5 +/-0 100 (2) (1)(14) Min Typ Load Imp. 8 Load Imp. 70 150 1.2 SP+/- Idle Rejection - ISD5100 SERIES (2) Max Units Conditions 1.0 V Peak-to-Peak (0 dB gain setting) mV Peak-to-Peak (0 dB gain setting Steps +0.5 dB (11) dB 1000 Hz –45 dB 0TLP Input setting Depending on AUX kΩ IN Gain ...
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... ANA OUT to SP+/- Cross R ANA OUT/(SP+/-) Talk +0.5 23.5 62.5 (2) Min Type (1)(14) 62.5 62.5 Noise – Rejection -40 1 ISD5100 SERIES sine wave input at V and V pins With 0TLP input to ANA IN, 6 (12) setting Guaranteed design mW Differential load at RMS 8Ω dB 0TLP ANA In input ...
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... Idle Channel Noise – ANA IN (AUX OUT) to AUX OUT C T AUX OUT to ANA OUT R AUX OUT/ANA Cross Talk OUT (14) VOLUME CONTROL Symbol Parameters A Output Gain OUT Tolerance for each step ISD5100 SERIES -65 (2) (1(14)) (2) Min Typ Max Units 1.0 5 100 1.2 62.5 -65 -65 (2) (1)(14) ...
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... HIGH period of the clock pulse, as changes in the data line at this time will be interpreted as a control signal the first page addressed. RAC RAC RACL ANA IN table ERIAL NTERFACE - 70 - ISD5100 SERIES and AUX IN table on pages 54 ANA IN table and AUX IN table Publication Release Date: Oct 31, 2008 Revision 1.42 ...
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... I sthe ‘master’ and the devices that are controlled by the master are the ‘slaves’. data line changed stable; of data data valid allowed 2 Bit transfer on the I C-Bus Definition of START and STOP conditions - 71 - ISD5100 SERIES SDA SCL P STOP condition Publication Release Date: Oct 31, 2008 Revision 1.42 ...
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... DATA OUTPUT BY RECEIVER SCL FROM MASTER S START condition LCD STATIC DRIVER RAM OR EEPROM GATE ARRAY ISD 5116 2 C-bus configuration using two microcontrollers not acknowledge Acknowledge on the I C-bus - 72 - ISD5100 SERIES acknowledge 8 9 dock pulse for acknowledgement Publication Release Date: Oct 31, 2008 Revision 1.42 ...
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... A common procedure in the ISD5100 Series is the reading of the Status Bytes. The Read Status condition in the ISD5100 Series is triggered when the Master addresses the chip with its proper Slave Address, immediately followed by the R/W bit set to a “1” and without the Command Byte being sent. ...
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... From Master Master Another common operation in the ISD5100 Series is the reading of digital data from the chip’s memory array at a specific address. This requires the I ISD5100 Series Slave device, and then receive data from the Slave in a single I accomplish this, the data direction R/W bit must be changed in the middle of the command. The ...
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... TYPICAL APPLICATION CIRCUIT The following typical application example on ISD5100 series is for references only. They make no representation or warranty that such applications shall be suitable for the use specified. It’s customer’s obligation to verify the design in its own system for the functionalities, voice quality, current consumption, and etc ...
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... H 0.520 0.528 0.536 13. 0.022 L 0.020 0.028 0.50 0.024 L 1 0.031 Y 0.000 0.004 0.00 θ ISD5100 SERIES P (TSOP) T ACKAGE YPE 1.20 0.15 1.00 1.05 0.20 0.27 0.15 0.21 11.90 11.80 8.10 8.00 13.60 13.40 0.55 0.60 0.70 0.80 ...
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... Nom M ax 0.528 0.535 0.465 0.469 0.315 0.319 0.006 0.009 0.011 0.039 0.041 0.022 0.028 0.008 - 77 - ISD5100 SERIES P (TSOP) T ACKAGE YPE ILLIM ETERS M in Nom 13.20 13.40 11.70 11.80 7.90 8.00 0.05 0.17 0.22 0.55 0.95 1. 0.50 0.55 0.10 Publication Release Date: Oct 31, 2008 Revision 1 ...
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... MALL UTLINE Nom Max 0.706 0.711 0.101 0.104 0.296 0.299 0.009 0.0115 0.016 0.019 0.050 0.406 0.410 0.032 0.040 - 78 - ISD5100 SERIES I C (SOIC) NTEGRATED IRCUIT MILLIMETERS Min Nom 17.81 17.93 2.46 2.56 7.42 7.52 0.127 0.22 0.35 0.41 1.27 10.16 10.31 ...
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... ISD5100 SERIES (PDIP) MILLIMETERS Nom 36.83 36.96 3.81 1.78 15.88 13.72 13.97 0.46 1.52 2.54 0.25 1.91 0° Publication Release Date: Oct 31, 2008 Revision 1.42 Max 1 ...
Page 80
... This figure reflects the current die thickness. Please contact Nuvoton as this thickness may change in the future. I NFORMATION V V SDA SCL SSD CCD SSD ≈ ISD5116 MIC - ANA OUT - SP - ANA OUT + ACAP - 80 - ISD5100 SERIES INT RAC CCD XCLK V SSA ≈ [2] V ANA IN CCA [2] V SSA AUX Publication Release Date: Oct 31, 2008 Revision 1.42 AUX OUT ...
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... ISD5116 Pad Coordinates (with respect to die center in µm) Pad Pad Name V Analog Ground SSA RAC Row Address Clock Interrupt INT XCLK External Clock Input V Digital Supply Voltage CCD V Digital Supply Voltage CCD SCL Serial Clock Line A1 Address 1 SDA Serial Data Address ...
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... This figure reflects the current die thickness. Please contact Nuvoton as this thickness may change in the future. I NFORMATION V SDA SCL V SSD SSD CCD ≈ ISD5108 MIC - ANA OUT - SP - ANA OUT + ACAP ISD5100 SERIES INT RAC CCD XCLK V SSA ≈ V [2] ANA IN CCA [2] AUX SSA Publication Release Date: Oct 31, 2008 Revision 1.42 AUX OUT ...
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... ISD5108 Pad Coordinates (with respect to die center in µm) Pad Pad Name V Analog Ground SSA RAC Row Address Clock Interrupt INT XCLK External Clock Input V Digital Supply Voltage CCD V Digital Supply Voltage CCD SCL Serial Clock Line A1 Address 1 SDA Serial Data Address ...
Page 84
... This figure reflects the current die thickness. Please contact Nuvoton as this thickness may change in the future. I NFORMATION V SDA SCL SSD SSD CCD ≈ ISD5104 MIC - ANA OUT - SP - ANA OUT + ACAP - 84 - ISD5100 SERIES V INT RAC CCD XCLK V SSA ≈ [2] V ANA IN CCA [2] AUX SSA Publication Release Date: Oct 31, 2008 Revision 1.42 AUX OUT ...
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... ISD5104 Pad Coordinates (with respect to die center in µm) Pad Pad Name V Analog Ground SSA RAC Row Address Clock Interrupt INT XCLK External Clock Input V Digital Supply Voltage CCD V Digital Supply Voltage CCD SCL Serial Clock Line A1 Address 1 SDA Serial Data Address ...
Page 86
... This figure reflects the current die thickness. Please contact Nuvoton as this thickness may change in the future. I NFORMATION V SDA SCL SSD SSD CCD ≈ ISD5102 MIC - ANA OUT - SP - ANA OUT + ACAP - 86 - ISD5100 SERIES V INT RAC CCD XCLK V SSA ≈ [2] V ANA IN CCA V [ AUX IN SSA Publication Release Date: Oct 31, 2008 Revision 1.42 AUX OUT ...
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... ISD5102 Pad Coordinates (with respect to die center in µm) Pad Pad Name V Analog Ground SSA RAC Row Address Clock Interrupt INT XCLK External Clock Input V Digital Supply Voltage CCD V Digital Supply Voltage CCD SCL Serial Clock Line A1 Address 1 SDA Serial Data Address ...
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... ORDERING INFORMATION ISD 5 1 Product Series ISD5100-Series Duration : min min min min When ordering the devices, please refer to the following valid ordering numbers. For the shaded part numbers, please contact the local Nuvoton Sales Representatives for availability. Duration ISD5102 Type Package ...
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... VERSION HISTORY VERSION DATE 0.1 Mar 2003 New data sheet for the ISD5100-Series 0.2 Oct 2003 Add I5102 and I5104 products Utilize TAD application in Functional Details Reserve Load Address feature for factory uses Simplify Playback mode AnaIn: add k Ω for Ra & Rb AuxIn: add k Ω ...
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... ISD prior to August, 1998. This datasheet and any future addendum to this datasheet is(are) the complete and controlling ISD product specifications. In the event any inconsistencies exist between the information in this and other product documentation the event that other product documentation contains information in addition to the information in this, the information contained herein supersedes and governs such other information in its entirety ...