CY4611B Cypress Semiconductor Corp, CY4611B Datasheet - Page 11

• Manufacturer Part Number: CY4611B
• Description: KIT USB TO ATA REFERENCE DESIGN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY4611B

• Main Purpose: Interface, USB 2.0 to ATA/CF
• Utilized Ic / Part: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A
• Silicon Manufacturer: Cypress
• Silicon Core Number: UDMA-100
• Kit Application Type: Interface
• Application Sub Type: USB To ATA
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EEPROM configuration format
AT2LP Configuration
EEPROM
Address
13-15
5-12
0x00
0x01
0x02
0x03
0x04
0x05
bATACBTaskFileWriteData
Reserved
I
I
APM Value
Unused
bVSCBSignature Value
Enable mode page 8
Disable wait for INTRQ
BUSY Bit Delay
Reserved
2
2
C EEPROM signature byte 0 I
C EEPROM signature byte 1 I
Field Name
For CY7C68300A compatibility mode, these bytes
should be set to 0x4D4D.
ATA Device Automatic Power Management Value. If an
attached ATA device supports APM and this field
contains other than 0x00, the AT2LP will issue a
SET_FEATURES command to Enable APM with this
value during the drive initialization process. Setting APM
Value to 0x00 disables this functionality. This value is
ignored with ATAPI devices.
Value in the first byte of the CBW CB field that
designates that the CB is to be decoded as vendor
specific ATA commands instead of the ATAPI command
block.
used.
Bits (7:6)
Bit (5)
Set to 1 to enable the write caching mode page (page
8). If this page is enabled, Windows will disable write
caching by default which will limit write performance.
Bit (4)
Set to 1 to poll status register rather than waiting for
INTRQ. Setting this bit to 1 will improve USB BOT test
results but may introduce compatibility problems with
some devices.
Bit (3)
Enables a delay of up to 120 ms at each read of the
DRQ bit where the device data length does not match
the host data length. This allows the
These bytes contain ATA register data used with ATA command or PIO write
operations. Only registers selected in bmATACBRegisterSelect are required to
hold valid data when accessed. The registers are as follows.
ATACB Address Offset 0x05 (0x3F6) Device Control
ATACB Address Offset 0x06 (0x1F1) Features
ATACB Address Offset 0x07 (0x1F2) Sector Count
ATACB Address Offset 0x08 (0x1F3) Sector Number
ATACB Address Offset 0x09 (0x1F4) Cylinder Low
ATACB Address Offset 0x0A (0x1F5) Cylinder High
ATACB Address Offset 0x0B (0x1F6) Device
ATACB Address Offset 0x0C (0x1F7) Command
These bytes must be set to 0x00 for ATACB commands.
2
2
C EEPROM signature byte 0. This byte must be 0x53.
C EEPROM signature byte 1. This byte must be 0x4B
See section 7
EZ-USB FX2LP USB to ATA Reference Design Notes
11
Field Description
for more detail on how this byte is
Required
Contents
0x4B
0x53
Suggested
Contents
0x00
0x80
0x24
0x07