CP2201EK Silicon Laboratories Inc, CP2201EK Datasheet - Page 81

KIT EVAL FOR CP2201 ETH CTRLR

CP2201EK

Manufacturer Part Number
CP2201EK
Description
KIT EVAL FOR CP2201 ETH CTRLR
Manufacturer
Silicon Laboratories Inc
Type
Controllers & Processorsr
Datasheets

Specifications of CP2201EK

Main Purpose
Interface, Ethernet Sensor
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
CP2200, CP2201
Primary Attributes
Temperature and Light Sensor
Secondary Attributes
Graphic User Interface
Interface Type
Ethernet
Product
Modules
Silicon Manufacturer
Silicon Labs
Silicon Core Number
CP2201
Silicon Family Name
CP220x
Kit Contents
CP2201 Evaluation Board, Power Adapter, CAT5e Ethernet Cable, CD-ROM, Quick-Start Guide
For Use With/related Products
CP2201
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
336-1316

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CP2201EK
Manufacturer:
SiliconL
Quantity:
8
Bit 15:
Bit 14:
Bits 13–5:Reserved. Read = varies; Must write 000000000b.
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
Reserved RANDRST
Bit15
R/W
R/W
Bit7
Reserved. Read = varies; Must write 0b.
RANDRST: Random Number Generator Reset
Writing a ‘1’ to this bit resets the random number generator within the transmit function.
LOOPBCK: Loopback Mode Enable Bit
Note: MAC Loopback Mode is independent of the physical layer loopback mode.
0: Normal operation.
1: MAC transmit data is internally looped back as MAC receive data.
TXPAUSE: TX Flow Control Enable Bit (Full-Duplex Only)
0: PAUSE control frames are blocked.
1: PAUSE control frames are allowed to pass through the MAC.
RXPAUSE: RX Flow Control Enable Bit (Full-Duplex Only)
0: PAUSE control frames received from the physical layer are ignored.
1: PAUSE control frames received from the physical layer are acted upon.
Reserved. Read = 0; Must write 0b.
RCVEN: Receive Enable
0: The MAC blocks control frames from reaching the receive interface. The MAC blocks all received
1: The MAC allows received packets to reach the receive interface.
Reserved
packets from the receive interface.
Bit14
R/W
R/W
Bit6
Indirect Register 1. MACCN: MAC Control Register
Bit13
R/W
R/W
Bit5
LOOPBCK TXPAUSE RXPAUSE Reserved
Bit12
R/W
R/W
Bit4
Bit11
R/W
R/W
Bit3
Rev. 1.0
Reserved
Bit10
R/W
R/W
Bit2
R/W
Bit9
R/W
Bit1
RCVEN
R/W
Bit8
R/W
Bit0
CP2200/1
Default Value
MACADDR:
0x8000
0x00
81

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