SD007EVK National Semiconductor, SD007EVK Datasheet - Page 7

• Manufacturer Part Number: SD007EVK
• Description: BOARD EVALUATION CLC007
• Manufacturer: National Semiconductor

Specifications of SD007EVK

• Design Resources: SD007EVK Schematic
• Main Purpose: Interface, Digital Cable Driver
• Utilized Ic / Part: CLC007
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

OUTPUT RISE AND FALL TIMES
Output load capacitance can significantly affect output rise
and fall times. The effect of load capacitance, stray or other-
wise, may be reduced by placing the output back-match
PCB Layout Recommendations
Printed circuit board layout affects the performance of the
CLC007. The following guidelines will aid in achieving satis-
factory device performance.
•
•
•
Use a ground plane or power/ground plane sandwich
design for optimum performance.
Bypass device power with a 0.01 µF monolithic ceramic
capacitor in parallel with a 6.8 µF tantalum electrolytic
capacitor located no more than 0.1” (2.5 mm) from the
device power pins.
Provide short, symmetrical ground return paths for:
FIGURE 7. Differential Input DC Coupled Output
FIGURE 8. Rise Time vs C
7
resistor close to the output pin and by minimizing all intercon-
necting trace lengths. Figure 8 shows the effect on risetime
of parallel load capacitance across a 150Ω load.
•
— inputs,
— supply bypass capacitors and
— the output load.
Provide short, grounded guard traces located
— under the centerline of the package,
— 0.1” (2.5 mm) from the package pins
— on both top and bottom of the board with connecting
vias.
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