SI3211PPTX-EVB Silicon Laboratories Inc, SI3211PPTX-EVB Datasheet - Page 138
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SI3211PPTX-EVB
Manufacturer Part Number
SI3211PPTX-EVB
Description
BOARD EVAL W/DISCRETE INTERFACE
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Specifications of SI3211PPTX-EVB
Main Purpose
Interface, Analog Front End (AFE)
Utilized Ic / Part
Si3211
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Si3210/Si3211
8.3.2. PCB Land Pattern: 16-Pin ESOIC
Figure 38 illustrates the recommended land pattern for the Si3201 SOIC-16 package. Table 53 lists the values for
the dimensions shown in the illustration.
138
Y2
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
Dimension
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ASME Y14.5M-1994.
3. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X175-17N.
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for
C1
X1
Y1
X2
mask and the metal pad is to be 60m minimum, all the way around the pad.
to assure good solder paste release.
Small Body Components.
E
Table 53. SOIC-16 PCB Land Pattern Dimensions
Figure 38. SOIC-16 PCB Land Pattern Drawing
Pin pad column spacing
Thermal pad length
Thermal pad width
Pin pad row pitch
Pin pad length
Pin pad width
Feature
Rev. 1.5
5.30
0.50
1.45
2.20
3.50
Min
1.27 BSC
Max
5.40
2.30
3.60
0.60
1.55
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