SI3000SSI-EVB Silicon Laboratories Inc, SI3000SSI-EVB Datasheet - Page 2

• Manufacturer Part Number: SI3000SSI-EVB
• Description: BOARD EVAL PARALLEL PORT SI3000
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3000SSI-EVB

• Main Purpose: Audio, CODEC
• Utilized Ic / Part: SI3000
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si3000SSI-EVB
Functional Description
The Si3000SSI-EVB provides an easy way to evaluate
the Si3000 solution.
This Si3000 device also supports the connection of
multiple devices on a single serial interface. The
evaluation board provides a straight forward means of
evaluating this feature.
The evaluation board consists of the Si30xxSSI-EVB
motherboard Figure 8/Figure 9 and the Si3000DC-EVB
daughter card Figure 3/Figure 4. The Si30xxSSI-EVB
can be used with other Silicon Laboratories daughter
cards, such as the Si3034DC-EVB. Contact a Silicon
Laboratories representative for more information.
In this document, the Si3000DC-EVB is occasionally
referred to “daughter card”, and the Si30xxSSI-EVB as
the “motherboard”. The Si3000SSI-EVB refers to the
system which consists of both the “motherboard” and
“daughter card.”
Motherboard–Daughter Card Connection
JP1 and JP2 on the daughter card are used to connect
to the motherboard.
JP1 is a 3x8 socket connection to the digital signals of
the Si3000. In addition, the V
motherboard (J2) is routed to this socket and supplies
the power to the daughter card. JP1 connects to JP7 of
the motherboard.
JP2 is a 2x5 socket connection to the Tip and Ring and
chassis ground of the line interface to the handset
selection circuitry. JP2 connects to JP8 of the
Si30xxSSI-EVB.
Power Supply
Power is supplied to the Si3000SSI-EVB by means of
J2, on the motherboard, when the board is used in
stand-alone mode. If multiple boards are cascaded
together, refer to the section on daisy-chain operation
for the power supply requirements.
J2 is a euroblock header which allows for connection to
a bench power supply. J2 provides the power for all
devices connected to the V
J2 can nominally be 3.3 V or 5 V. Note that U3 and U4
can operate from either 3.3 V or 5 V. If Y1 is used, it
must support 3.3 V operation if V
J3 is used to supply power to V
used in conjunction with the Si3000DC-EVB.
Diodes D4 and D5 on the motherboard are used to
protect the Si3000SSI-EVB against over-voltage or
accidental terminal reversal. They are rated at 6.8 V.
2
D
node.
D
A
. However, V
= 3.3 V.
D
power of the
Preliminary Rev. 0.7
A
is not
Clock Generation
The Si3000 requires an MCLK input. The EVB provides
two options for this requirement. MCLK can be provided
via pin 1 of JP4 (on the motherboard) from the target
system or from an oscillator installed in Y1 (on the
motherboard). JP3 (on the motherboard) selects the
MCLK source to the Si3000. In the Y1 position, the
oscillator installed in Y1 is connected. If 3.3 V is the VD
supply, Y1 must be a 3.3 V oscillator. In the JP4
position, the clock on JP4 is connected. Valid MCLK
frequency ranges from 1 to 60 MHz.
If multiple boards are cascaded together, refer to the
section on daisy-chain operation. Only the master board
will need an MCLK from Y1 or JP4.
Optional Call Progress Speaker
This feature on the Si30xxSSI-EVB is used in conjunc-
tion with the Si3034/35 evaluation boards, but is not uti-
lized by the Si3000.
Reset Circuit
The Si3000 requires an active low pulse on RESET
following power up and whenever all registers need to
be reset. Typically, the target system generates this
signal and supplies it on pin 9 of JP4 (on the
motherboard).
Si3000SSI-EVB includes a reset push button, SW1, that
is a logic OR (active low) with the reset signal from the
target system. U4 (of the motherboard) provides the
reset logic and serves as a buffer. This circuit is not
necessary in a production design.
If multiple EVBs are cascaded together, the reset signal
should be generated by the master board. Using the
SW1 pushbutton on slave boards will only reset that
slave board and slave boards further down the chain.
Serial Modes
The Si3000 supports two different serial modes for a
glueless interface to many standard DSP and ASIC
serial ports. The serial mode of the Si3000 can be
selected by JP1 and JP2 on the motherboard.
GND
GND
M1
V
V
D
D
Table 1: Si3000 Serial Modes
GND
GND
M0
V
V
For
D
D
development
FSYNC pulse starts data frame
FSYNC frames data
Slave Operation
Reserved
Mode
purposes,
the