SI3215MPPQ1-EVB Silicon Laboratories Inc, SI3215MPPQ1-EVB Datasheet - Page 32

• Manufacturer Part Number: SI3215MPPQ1-EVB
• Description: BOARD EVAL W/SI3201 INTERFACE
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3215MPPQ1-EVB

• Main Purpose: Interface, Analog Front End (AFE)
• Utilized Ic / Part: Si3215
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si3215
2.3.5. DC-DC Converter Enhancements
The Si3215 supports two enhancements to the dc-dc
converter. The first is a multi-threshold error control
algorithm that enables the dc-dc converter to adjust
more quickly to voltage changes. This option is enabled
by setting DCSU = 1 (direct Register 108, bit 5). The
second enhancement is an audio band filter that
removes audio band noise from the dc-dc converter
control loop. This option is enabled by setting DCFIL = 1
(direct Register 108, bit 1).
2.3.6. DC-DC Converter During Ringing
When the ProSLIC enters the ringing state, it requires
voltages well above those used in the active mode. The
voltage to be generated and regulated by the dc-dc
converter during a ringing burst is set using the V
register (direct Register 74). V
0 and –94.5 V in 1.5 V steps. To avoid clipping the
ringing signal, V
amplitude. At the end of each ringing burst, the dc-dc
converter adjusts back to active state regulation as
described above.
32
Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped
DC-DC Converter Min. Off Time
DC-DC Converter PWM Period
DC-DC Converter Calibration
High Battery Voltage—V
DC-DC Converter Power-Off
Low Battery Voltage—V
directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through
31).
Enable/Status
Parameter
Control
V
BATH
OV
must be set larger than the ringing
Table 26. Associated Relevant DC-DC Converter Registers
BATL
BATH
BATH
can be set between
(0 to 1.892 µs) + 4 ns
0 to 15.564 µs
0 to –94.5 V
0 to –94.5 V
0 to –13.5 V
0 to –9 V or
Range
N/A
N/A
BATH
Rev. 0.92
2.4. Tone Generation
Two digital tone generators are provided in the ProSLIC.
They allow the generation of a wide variety of single- or
dual-tone frequency and amplitude combinations and
spare the user the effort of generating the required
POTS signaling tones on the PCM highway. DTMF, FSK
(caller ID), call progress, and other tones can all be
generated on-chip. The tones can be sent to either the
receive or transmit paths (see Figure 22 on page 40).
2.4.1. Tone Generator Architecture
A simplified diagram of the tone generator architecture
is shown in Figure 18. The oscillator, active/inactive
timers, interrupt block, and signal routing block are
connected to give the user flexibility in creating audio
signals. Control and status register bits are placed in the
figure to indicate their association with the tone
generator architecture. These registers are described in
more detail in Table 27.
Resolution
61.035 ns
61.035 ns
1.5 V
1.5 V
1.5 V
N/A
N/A
Register Bit
DCTOF[4:0]
VBATH[5:0]
VMIND[3:0]
VBATL[5:0]
DCN[7:0]
DCCAL
DCOF
VOV
Indirect Register 64
Direct Register 92
Direct Register 75
Direct Register 14
Direct Register 93
Direct Register 93
Direct Register 74
Direct Register 66
Location