SI3056SSI1-EVB Silicon Laboratories Inc, SI3056SSI1-EVB Datasheet - Page 77

• Manufacturer Part Number: SI3056SSI1-EVB
• Description: BOARD EVAL SI3056/SI3019 SSI
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3056SSI1-EVB

• Main Purpose: Telecom, Data Acquisition Arrangement (DAA)
• Utilized Ic / Part: Si3056
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Register 43. Line Current/Voltage Threshold Interrupt (Si3019 Line-Side Device Only)
Reset settings = 0000_0000
Register 44. Line Current/Voltage Threshold Interrupt Control (Si3019 Line-Side Device Only)
Reset settings = 0000_0000
Bit
7:0
Bit
7:4
Name
Name
Type
Type
3
2
1
0
Bit
Bit
Reserved Read returns zero.
CVT[7:0]
Name
Name
CVM
CVS
CVP
CVI
D7
D7
Current/Voltage Threshold.
Determines the threshold at which an interrupt is generated from either the LCS or LVS regis-
ter. Generate this interrupt to occur when the line current or line voltage rises above or drops
below the value in the CVT[7:0] register.
Current/Voltage Interrupt.
0 = The current / voltage threshold has not been crossed.
1 = The current / voltage threshold is crossed. If the CVM and INTE bits are set, a hardware
interrupt occurs on the AOUT/INT pin. Once set, this bit must be written to 0 to be cleared.
Current/Voltage Select.
0 = The line current shown in the LCS2 register generates an interrupt.
1 = The line voltage shown in the LVS register generates an interrupt.
Current/Voltage Interrupt Mask.
0 = The current / voltage threshold being triggered does not cause a hardware interrupt on the
AOUT/INT pin.
1 = The current / voltage threshold being triggered causes a hardware interrupt on the AOUT/
INT pin.
Current/Voltage Interrupt Polarity.
0 = The current / voltage threshold is triggered by the absolute value of the number in either
the LCS2 or LVS register falling below the value in the CVT[7:0] register.
1 = The current / voltage threshold is triggered by the absolute value of the number in the
either the LCS2 or LVS register rising above the value in the CVT[7:0] Register.
D6
D6
D5
D5
D4
D4
CVT[7:0]
R/W
R/W
CVI
D3
D3
Rev. 1.05
CVS
R/W
D2
D2
Function
Function
CVM
R/W
D1
D1
CVP
R/W
D0
D0
Si3018/19/10
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