SI3050PPT2-EVB Silicon Laboratories Inc, SI3050PPT2-EVB Datasheet - Page 3

• Manufacturer Part Number: SI3050PPT2-EVB
• Description: BOARD EVAL FOR DAA SI3050/SI3008
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3050PPT2-EVB

• Main Purpose: Telecom, Data Acquisition Arrangement (DAA)
• Utilized Ic / Part: Si3050
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2. Configuring the Si-LINK
The Si-LINK motherboard is used to interface the
Si3050 to a PC or other audio system for easy
evaluation. It uses an FPGA to translate the parallel port
interface to either SPI/PCM, SPI-only, or GCI to
communicate with the Si3050.
When in SPI/PCM mode, the PCM audio data and SPI
control data are communicated from the controlling PC
using the aforementioned software. This mode allows
the user to evaluate the DAA without any lab equipment
other than a PC.
By selecting SPI-only operation, the PC is still used to
control the DAA through the SPI bus, but the PCM
audio data is routed from an external source. This
external source may be an Audio Precision system
using the P1 and P2 headers or a PCM highway using
the BNC connectors, J5–J8 (not populated).
To evaluate the Si3050’s operation with the GCI
interface, the PC may be used to send the audio data
and control. The FPGA performs the necessary
translation to communicate to the Si3050 in this mode.
The fourth mode of operation is the pass-thru mode. In
this mode, the FPGA is only used to route the GCI bus
to the Audio Precision or BNC headers on the Si-LINK
board. In this mode, a PC is not required to control the
evaluation platform.
3. Configuring the Si3050DC-EVB
The Si3050DC-EVB has six jumpers. The first five
control the boot-strap options for configuring the
Si3050. The default state is set to allow the Si3050 to be
controlled using the SPI bus. See Figure 1.
0
Pass-Thru
CS
SPI/PCM
SPI-Only
Mode
Figure 1. SPI Control Mode Default State
GCI
1
0 SCLK 1
JP3 (Source)
0 SDO 1
0
1
0
1
0 SDI_THRU 1
JP4 (Format)
0
0
1
1
0
SDI
Rev. 1.0
1
By changing the jumper configuration prior to powering
the board, the mode of the board can be set according
to Tables 1–3.
JP10 is the sixth jumper on the Si3050DC-EVB. Moving
this jumper to the INT position routes pin 9 of the
Si3050 to the Si-LINK motherboard. When the jumper is
in the AOUT position, this signal is routed to the optional
call progress speaker system, which is not populated by
default on the evaluation platform. Refer to the AOUT
PWM circuit in the Si3050 data sheet for values used to
populate this circuit.
Table 2. Pin Functionality in PCM or GCI
Highway Mode
Pin Name
SDI_THRU SPI Data Through-
SCLK
SDI
SDO
CS
FSYNC
PCLK
DTX
DRX
Note: This table denotes pin functionality after the rising
Table 1. PCM or GCI Highway Mode Selection
Note: Values shown are the states of the pins at the
SCLK
edge of RESET and mode selection.
1
0
0
rising edge of RESET.
PCM Mode
put pin for Daisy
Chaining Operation
(Connects to the SDI
pin of the subse-
quent device in the
daisy chain)
SPI Clock Input
SPI Serial Data Input B1/B2 Channel
SPI Serial Data Out-
put
SPI Chip Select
PCM Frame Sync
Input
PCM Input Clock
PCM Data Transmit
PCM Data Receive
SDI
Si3050PPT-EVB
X
0
1
B2 Channel used
B1 Channel used
Mode Selected
PCM Mode
GCI Mode,
GCI Mode,
GCI Mode
Sub-frame
Selector, bit 2
PCM/GCI Mode
Selector
Selector
Sub-frame
Selector, bit 1
Sub-frame
Selector, bit 0
GCI Frame Sync
Input
GCI Input Clock
GCI Data Transmit
GCI Data Receive
3