SI3050PPT1-EVB Silicon Laboratories Inc, SI3050PPT1-EVB Datasheet
SI3050PPT1-EVB
Specifications of SI3050PPT1-EVB
Related parts for SI3050PPT1-EVB
SI3050PPT1-EVB Summary of contents
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Description The Si3050PPT-EVB provides the telecommunications system engineer an easy way to evaluate the functionality of Silicon Laboratories’ Si3050/Si3019 ...
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Si3050PPT-EVB 1. Functional Description The Si3050PPT-EVB provides the telecommunications system engineer an easy way to evaluate the Si3059/19 solution. Silicon Labs’ DAAs are integrated direct access arrangements that provide a digital, low-cost, solid-sate interface to worldwide telephone lines. Through the ...
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Configuring the Si-LINK The Si-LINK motherboard is used to interface the Si3050 other audio system for easy evaluation. It uses an FPGA to translate the parallel port interface to either SPI/PCM, SPI-only, or GCI to ...
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Si3050PPT-EVB Table 3. GCI Mode Sub-Frame Selection GCI Subframe 0 Selected (Voice channels 1–2) GCI Subframe 1 Selected (Voice channels 3–4) GCI Subframe 2 Selected (Voice channels 5–6) GCI Subframe 3 Selected (Voice channels 7–8) GCI Subframe 4 Selected (Voice ...
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Evaluation Software The Si3050PPT-EVB includes an easy-to-use graphical interface for controlling the evaluation platform. This software allows the system designer to characterize the Si3050 DAA performance without constructing any custom hardware. The evaluation software includes the following features: Ability ...
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Si3050PPT-EVB Figure 2. Si3050PPT-EVB Evaluation Software in the DSP Mode Control and 5.2. DSP Mode and RCV Source Control View The user interface in the DSP Mode and RCV Source Control view for the Si3050PPT_EVB software is shown in Figure ...
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Figure 3. Si3050PPT-EVB Evaluation Software in the Audio Data Monitoring View 5.3. Audio Data Monitoring View The audio data monitoring view is discussed in the following sections. 5.3.1. Receive Audio Data of Channel# Allows selection of channel to control and ...
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Si3050PPT-EVB line monitoring mode configures the DAA to the line monitoring state. RX Gain (dB): Selects the receive path gain/ attenuation. RX Mute: Mutes the receive path Ring Detect Mode: Allows selection of full-wave or half-wave ring detection. 5.3.4. Dialer ...
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Figure 4. Si3050PPT-EVB Evaluation Software in the Register Table Display View 5.4. Register Table Display View The DAA Register view allows the Si3050 DAA registers to be read or written. The user interface for the DAA Register view is shown ...
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Si3050PPT-EVB 5.5. Advanced Configuration Advanced configuration of the application software is accomplished by using the “Configure DAA” selection in the “Configure” menu. The configuration panel is shown in Figure 5. The panel contents are detailed in the following list: FFT ...
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Signal Flow Diagrams The signal flow diagrams of the application software shown in Figure 6 on page 11 and Figure 7 on page 12 assist users with programming DAA. 5.7. Si3050 Signal Path Control PCML: Turns on/off the PCML ...
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Si3050PPT-EVB 5.8. Si3019 Signal Path Control AL: Turns on/off AL bit on Register 2, bit 3 HBE: Turns on/off HBE bit on Register 2, bit 1 RXE: Turns on/off RXE bit on Register 2, bit 0 IDL: Turns on/off IDL ...
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Transhybrid Loss Calculation When “Transhybrid Loss Calculation” is selected, the Si3050PPT-EVB software will drive a signal with different frequencies and measure the transhybrid loss based on the following equation 20Log(TXpk-pk/ RXpk-pk). Frequencies used to measure this start ...
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Si3050PPT-EVB Figure 9. Ringing 14 5.10. Ringing RNGV-Enable: Turns on/off RNGV bit on Register 24, bit7 RAS[5:0]: Update RAS bits on Register 24 RMX[5:0]: Update RMX bits on Register 22 RCC[2:0]: Update RCC bits on Register 23 RTO[3:0]: Update RTO ...
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Typical Application Diagram ...
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Si3050PPT-EVB VDD /TGDE /RG Figure 11. Si3050-EVB Daughter Card Typical Application Circuit ( RING TIP Figure 12. Si3050-EVB Daughter Card Typical Application Circuit ( VDD R106 R106 /TGD VBLO R105 R105 ...
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Si3050PPT-EVB Rev. 1.0 17 ...
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Si3050PPT-EVB 7. Bill of Materials: Si3050PPT-EVB Daughter Card Item QTY Reference Value 1 2 C1 C5,C6,C50,C51 0 2 C9,C8 ...
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OUT GND 8 7 OUT2 GND2 11 4 VCC Si3050PPT-EVB ...
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Si3050PPT-EVB ...
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VCC50 GND52 VCC127 GND129 VCC16 GND15 VCC85 VCCIO(8) 134 VCC134 VCCIO(7) 115 VCCIO(6) 94 VCC94 VCCIO(5) 71 VCCIO(4) 61 VCC61 VCCIO(3) 45 VCCIO(2) 24 VCC24 VCCIO(1) 5 VCCINT(6) 127 VCC127 VCCINT(5) 103 VCCINT(4) 85 VCC85 VCCINT(3) 75 VCCINT(2) 50 VCC50 ...
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Si3050PPT-EVB Return Return Return Return Source VRNGSOURCE Battery 22 Protection 3 Protection 2 1 Protection RNG GROUND 3 GROUND 2 GROUND 1 Battery Low 3 Battery High 2 Ringing 1 Rev. 1.0 GND 2 ...
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Bill of Materials: Si3050PPT-EVB Motherboard Reference Value C1 4.7uF C2,C6,C11,C13,C15,C17, 10uF C19,C21,C24,C26 C3 470 uF C4 .33uF C5,C7 .1uF C8,C10,C12,C14,C16,C18, 0.1 uF C20,C23,C25 C9 1uF C22 0.1 uF D1,D2 LED 4pack D3,D4,D5,D6 DIODE D8 DIODE FB1 Ferrite Bead on ...
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Si3050PPT-EVB Figure 20. Daughter Card Secondary Side 24 Figure 18. Daughter Primary Assembly Figure 19. Daughter Card Primary Side Rev. 1.0 ...
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Si3050PPT-EVB Rev. 1.0 25 ...
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Si3050PPT-EVB 26 Rev. 1.0 ...
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Si3050PPT-EVB Rev. 1.0 27 ...
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OCUMENT HANGE IST Revision 0.2 to Revision 0.3 Updated schematics Updated BOMs Updated layers Revision 0.3 to Revision 0.4 "1. Functional Description" on page 2: deleted text Table 3 moved Figure 4 updated Figure 8 updated "5.8. ...
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N : OTES Si3050PPT-EVB Rev. 1.0 29 ...
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