SI3056PPT3-EVB Silicon Laboratories Inc, SI3056PPT3-EVB Datasheet
SI3056PPT3-EVB
Specifications of SI3056PPT3-EVB
Related parts for SI3056PPT3-EVB
SI3056PPT3-EVB Summary of contents
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Features Complete DAA includes the following: Programmable line interface AC termination DC termination Ring detect threshold Ringer impedance 80 ...
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Si3018/19/10 2 Rev. 1.05 ...
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Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . ...
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Si3018/19/10 9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Electrical Specifications Table 1. Recommended Operating Conditions 1 Parameter Ambient Temperature 3 Si3056 Supply Voltage, Digital Notes: 1. The Si3056 specifications are guaranteed when the typical application circuit (including component tolerance) and the Si3056 and any Si3018 or Si3019 ...
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Si3018/19/10 Table 2. Loop Characteristics = = see (V 3 ° Parameter Symbol DC Termination Voltage V DC Termination Voltage V DC Termination Voltage V DC Termination Voltage V DC Termination ...
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Table 3. DC Characteristics 3 ° Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current 1 ...
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Si3018/19/10 Table 4. AC Characteristics (V = 3 °C; see Figure 17 on page 18 Parameter 1 Sample Rate 1 PLL Output Clock Frequency Transmit Frequency Response Receive Frequency Response ...
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Table 4. AC Characteristics (Continued 3 °C; see Figure 17 on page 18 Parameter Receive Total Harmonic 8,9 Distortion Receive Total Harmonic 8,9 Distortion Dynamic Range (caller ID ...
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Si3018/19/10 Table 5. Absolute Maximum Ratings Parameter DC Supply Voltage Input Current, Si3056 Digital Input Pins Digital Input Voltage Operating Temperature Range Storage Temperature Range Note: Permanent device damage can occur if the above absolute maximum ratings are exceeded. Restrict ...
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Table 7. Switching Characteristics—Serial Interface (Master Mode, DCE = 3 ° pF Parameter Cycle time, SCLK SCLK Duty Cycle Delay Time, SCLK↑ to ...
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Si3018/19/10 Table 8. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = Charge Pump 3 1,2 Parameter Cycle Time, SCLK SCLK Duty Cycle Delay Time, SCLK ↑ to ...
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Table 9. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = 3 ° pF Parameter Cycle Time, SCLK SCLK Duty ...
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Si3018/19/10 Table 10. Switching Characteristics—Serial Interface (Slave Mode, DCE = 1, FSD = Charge Pump 3 Parameter Cycle Time, MCLK Setup Time, FSYNC ↑ before MCLK ↓ * Delay ...
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Table 11. Digital FIR Filter Characteristics—Transmit and Receive (V = 3.0 to 3.6 V, Sample Rate = 8 kHz Parameter Passband (0.1 dB) Passband (3 dB) Passband Ripple Peak-to-Peak Stopband Stopband Attenuation Group Delay Note: Typical FIR filter ...
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Si3018/19/10 Figure 7. FIR Receive Filter Response Figure 8. FIR Receive Filter Passband Ripple For Figures 7–10, all filter plots apply to a sample rate kHz. 16 Figure 9. FIR Transmit Filter Response Figure 10. FIR ...
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Figure 11. IIR Receive Filter Response Figure 12. IIR Receive Filter Passband Ripple Figure 13. IIR Transmit Filter Response Si3018/19/10 Figure 14. IIR Transmit Filter Passband Ripple Figure 15. IIR Receive Group Delay Figure 16. IIR Transmit Group Delay Rev. ...
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Si3018/19/10 2. Typical Application Schematic 18 Rev. 1.05 ...
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Bill of Materials Component(s) C1 C5, C6, C50, C51 C7 C8, C9 C10 3 C30, C31 Not installed, 120 pF, 250V, X7R, ±10% 2 D1, D2 Dual Diode, 225 mA, 300 V, CMPD2004S FB1, FB2 ...
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Si3018/19/10 4. AOUT PWM Output Figure 18 illustrates an optional circuit to support the pulse width modulation (PWM) output capability of the Si3056 for call progress monitoring purposes. Set the PWME bit (Register 1, bit 3) to enable this mode. ...
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Functional Description The Si3056 is an integrated direct access arrangement (DAA) that provides a programmable line interface to meet global telephone line interface requirements. The Si3056 implements Silicon Laboratories isolation technology and offers the highest level of integration by ...
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Si3018/19/10 Chipset System-Side Part # Line-Side Part # Global DAA Digital Interface Power Supply Max Modem Connect Rate Data Bus Width Control Register Addressing Max Sampling Frequency AC Terminations Programmable Gain Loop Current Monitoring Line Voltage Monitoring Polarity Reversal Detection ...
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Table 15. Country Specific Register Settings Register 16 31 Country OHS OHS2 Argentina Australia 1 0 Austria 0 1 Bahrain 0 1 Belgium 0 1 Brazil 0 0 Bulgaria 0 1 Canada 0 0 Chile 0 0 ...
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Si3018/19/10 Table 15. Country Specific Register Settings (Continued) Register 16 31 Country OHS OHS2 Lebanon 0 1 Luxembourg 0 1 Macao Malaysia 0 0 Malta 0 1 Mexico 0 0 Morocco 0 1 Netherlands 0 1 New ...
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Power Supplies The Si3056 system-side device operates from a 3.0– 3.6 V power supply. The Si3056 input pins are 5 V tolerant. The Si3056 output pins only drive 3.3 V. The line-side device derives its power from two sources: ...
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Si3018/19/10 These registers can help determine the following: When on-hook, detect if a line is connected. When on-hook, detect if a parallel phone is off-hook. When off-hook, detect if a parallel phone goes on or off-hook. Detect if enough loop ...
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Several events occur in the DAA when the OFHK pin is asserted or the OH bit is set. There is a 250 µ s latency to allow the off-hook command to be communicated to the line-side device. Once the line-side ...
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Si3018/19/10 TBR21 DCT Mode .015 .02 .025 .03 .035 .04 .045 .05 .055 .06 Loop Current (A) Figure 21. TBR21 Mode I/V Characteristics, DCV[1:0] = 11, MINI[1:0] = 00, ILIM = ...
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There are two selections that are useful for satisfying non-standard ac termination requirements. The 350 Ω + (1000 Ω || 210 nF) impedance selection is the ANSI/ EIA/TIA 464 compromise impedance network for trunks. The last ac termination selection, ACIM[3:0] ...
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Si3018/19/10 while the RNG1-RNG2 voltage is between the thresholds. When the ring becomes positive, DTX transitions to +32767. When the ring signal goes near 0, DTX remains near 1228. As the ring becomes negative, the DTX transitions to –32768. This ...
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Pulse Dialing and Spark Quenching Pulse dialing results from going off- and on-hook to generate make and break pulses. The nominal rate is 10 pulses per second. Some countries have strict specifications for pulse fidelity that include make and ...
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Si3018/19/ TIP From Line C3 RING Figure 22. Billing Tone Filter L1 must carry the entire loop current. The series resistance of the inductors is important to achieve a narrow and deep notch. This design has more ...
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The host processor must detect the presence of this tone. 2. The DAA must then check for another parallel device on the same line. This is accomplished by briefly going on-hook, measuring the line voltage, and then returning ...
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Si3018/19/10 O ff-Hook Counter LIN E and C alibration O n-H ook (402. nom inally [ [ ...
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Overload Detection The Si3056 can be programmed to detect an overload condition that exceeds the normal operating power range of the DAA circuit. To use the overload detection feature, the following steps should be followed: 1. Set the OH ...
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Si3018/19/10 5.24. Filter Selection The Si3056 supports additional filter selections for the receive and transmit signals as defined in Table 11 and Table 12 on page 15. The IIRE bit (Register 16, bit 4) selects between the IIR and FIR ...
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PLL Lock Times The Si3056 changes sample rates quickly. However, lock time varies based on the programming of the clock generator. The following relationships describe the boundaries on PLL locking time: PLL1 lock time < PLL2 lock ...
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Si3018/19/10 provides software control of the secondary frames alternative method, the FC pin can serve as a hardware flag for requesting a secondary frame. The external DSP can turn on the 16-bit TX mode by setting the SB ...
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SRC[3:0] bits (Register 7, bits programmed with the proper sample rate value before the sampled line data is valid. The SCLK pin of the slave connect in this configuration. The delay between FSYNC input and delayed frame ...
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Si3018/19/10 passes through the internal filters and transmitted on SDO which introduces approximately attenuation on the SDI signal received. The group delay of both transmit and receive filters exists between SDI and SDO. Clearing the PDL bit disables this mode ...
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Revision Identification With the Si3056 the system designer can determine the revision of the Si3056 and/or the line-side device. The REVA[3:0] bits (Register 11, bits 3:0) identify the revision of the Si3056. The REVB[3:0] bits (Register 13, bits 3:0) ...
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Si3018/19/10 Com m unications Fram e 1 (CF1) FSYNC Prim ary FC 0 D15–D0 SDI XMT Data SDO RCV Data 16 SCLKS 128 SCLKS Figure 28. Hardware FC/RGDT Secondary Request FSYNC (mode 0) FSYNC (mode 1) SDI SDO Figure 29. ...
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FSYNC (mode 0) FSYNC (mode 1) SDI R/W SDO Figure 30. Secondary Communication Data Format—Write Cycle Master Serial Mode 1 Reg 14: NSLV = 1, SSEL = 2, FSD = 0, DCE = 1 Slave 1 Serial Mode 2 Reg ...
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Si3018/19/10 Master Serial Mode 1 Reg 14: NSLV = 1, SSEL = 2, FSD = 1, DCE = 1 Slave 1 Serial Mode 2 Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1 ...
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Si3018/19/10 Rev. 1.05 45 ...
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Si3018/19/10 M aster Serial M ode 0 Reg 14: NSLV = 1, SSEL = 2, FSD = 0, DCE = 1 Slave 1 Serial M ode 2 Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, ...
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Host SCLK SDO SDI FSYNC INTO 47 kΩ 47 kΩ VCC 47 kΩ Figure 36. Typical Connection for Multiple DAAS Rev. 1.05 Si3018/19/10 MCLK Si3056—Master MCLK SCLK SDI SDO FSYNC FC/RGDT RGDT/FSD/M1 VCC M0 47 kΩ Si3056—Slave 1 MCLK NC ...
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Si3018/19/10 6. Control Registers Register Name 1 Control 1 2 Control 2 3 Interrupt Mask 4 Interrupt Source 5 DAA Control 1 6 DAA Control 2 7 Sample Rate Control 8 PLL Divide N 9 PLL Divide M 10 DAA ...
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Register 1. Control 1 Bit Name SR PWMM[1:0] Type R/W Reset settings = 0000_0000 Bit Name 7 SR Software Reset Enables the DAA for normal operation Sets all registers to their reset value. ...
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Si3018/19/10 Register 2. Control 2 Bit Name INTE INTP Type R/W R/W Reset settings = 0000_0011 Bit Name 7 INTE Interrupt Pin Enable The AOUT/INT pin functions as an analog output for call progress monitoring ...
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Register 3. Interrupt Mask Bit Name RDTM ROVM FDTM Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 RDTM Ring Detect Mask ring signal does not cause an interrupt on the AOUT/INT ...
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Si3018/19/10 Register 4. Interrupt Source Bit Name RDTI ROVI FDTI Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 RDTI Ring Detect Interrupt ring signal is not occurring ring ...
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Bit Name 1 DLCSI Delta Loop Current Sense Interrupt 0 = The LCS bits have not changed value The LCS bits have changed value; a hardware interrupt occurs on the AOUT/INT pin. This bit must be written to ...
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Si3018/19/10 Register 6. DAA Control 2 Bit Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4 PDL Powerdown Line-Side Device Normal operation. Program the clock generator before clearing this bit. ...
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Register 8. PLL Divide N Bit Name Type Reset settings = 0000_0000 (serial mode 0, 1) Reset settings = 0001_0011 (serial mode 2) Bit Name 7:0 N[7:0] PLL N Divider. Contains the (value –1) for determining the ...
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Si3018/19/10 Register 11. System-Side and Line-Side Device Revision Bit Name LSID[3:0] Type R Reset settings = xxxx_xxxx Bit Name 7:4 LSID[3:0] Line-Side ID Bits. These four bits will always read one of the following values depending on ...
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Register 13. Line-Side Device Revision Bit Name 0 Type Reset settings = xxxx_xxxx Bit Name 7 Reserved Read returns zero This bit always reads a zero. 5:2 REVB[3:0] Line-Side Device Revision. Four-bit value indicating the ...
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Si3018/19/10 Register 14. Serial Interface Control Bit Name NSLV[2:0] Type R/W Reset settings = 0000_0000 (serial mode 0,1) Reset settings = 0011_1101 (serial mode 2) Bit Name 7:5 NSLV[2:0] Number of Slaves devices. 000 = 0 slaves. ...
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Register 15. TX/RX Gain Control 1 Bit Name TXM ATX[2:0] Type R/W R/W Reset settings = 0000_0000 Bit Name 7 TXM Transmit Mute Transmit signal is not muted Mutes the transmit signal. 6:4 ...
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Si3018/19/10 Register 16. International Control 1 Bit Name ACT2 OHS ACT Type RW R/W R/W Reset settings = 0000_0000 Bit Name 7 ACT2 AC Termination Select 2 (Si3018 line-side device only). Works with the ACT bit to ...
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Register 17. International Control 2 Bit Name CALZ MCAL CALD Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 CALZ Clear ADC Calibration Normal operation Clears the existing calibration data. This ...
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Si3018/19/10 Register 18. International Control 3 Bit Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero or one. 1 RFWE Ring Detector Full-Wave Rectifier Enable. When RNGV (Register 24) is disabled, this bit ...
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Register 19. International Control 4 Bit Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 OVL Receive Overload Detect. This bit has the same function as ROV in Register 17, but clears ...
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Si3018/19/10 Register 20. Call Progress Receive Attenuation Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 ARM[7:0] AOUT Receive Path Attenuation. When decremented from the default setting, these bits linearly attenuate the AOUT receive path signal ...
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Register 22. Ring Validation Control 1 Bit Name RDLY[1:0] Type R/W Reset settings = 1001_0110 Bit Name 7:6 RDLY[1:0] Ring Delay Bits 1 and 0. These bits, in combination with the RDLY[2] bit (Register 23), set the ...
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Si3018/19/10 Register 23. Ring Validation Control 2 Bit Name RDLY[2] RTO[3:0] Type R/W Reset settings = 0010_1101 Bit Name 7 RDLY[2] Ring Delay Bit 2. This bit, in combination with the RDLY[1:0] bits (Register 22), set the ...
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Register 24. Ring Validation Control 3 Bit Name RNGV Type R/W R Reset settings = 0001_1001 Bit Name 7 RNGV Ring Validation Enable Ring validation feature is disabled Ring validation feature is enabled ...
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Si3018/19/10 Register 25. Resistor Calibration Bit Name RCALS RCALM RCALD Type R R/W R/W Reset settings = xx0x_xxxx Bit Name 7 RCALS Resistor Auto Calibration Resistor calibration is not in progress Resistor calibration ...
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Register 26. DC Termination Control Bit Name DCV[1:0] MINI[1:0] Type R/W Reset settings = 0000_0000 Bit Name 7:6 DCV[1:0] TIP/RING Voltage Adjust. Adjust the voltage on the DCT pin of the line-side device, which affects the TIP/RING ...
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Si3018/19/10 Register 27. Reserved Bit Name Type Reset settings = xxxx_xxxx Bit Name 7:0 Reserved Do not read or write. Register 28. Loop Current Status Bit Name Type Reset settings = 0000_0000 Bit Name ...
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Register 30. AC Termination Control (Si3019 line-side device only) Bit Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 FULL2 Enhanced Full Scale (2X) Transmit and Receive Mode (Si3019 line-side Revision E ...
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Si3018/19/10 Register 31. DAA Control 3 Bit Name FULL FOH[1:0] Type R/W R/W Reset settings = 0010_0000 Bit Name 7 FULL Full Scale Transmit and Receive Mode (Si3019 line-side device only Default Transmit/receive ...
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Register 32-37. Reserved Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 Reserved Read returns zero. Register 38. TX Gain Control 2 (Si3019 Line-Side Device Only) Bit Name Type Reset settings = 0000_0000 ...
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Si3018/19/10 Register 39. RX Gain Control 2 (Si3019 Line-Side Device Only) Bit Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 RGA2 Receive Gain or Attenuation Incrementing the RXG2[3:0] ...
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Register 40. TX Gain Control 3 (Si3019 Line-Side Device Only) Bit Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 TGA3 Transmit Gain or Attenuation Incrementing the TXG3[3:0] bits ...
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Si3018/19/10 Register 41. RX Gain Control 3 (Si3019 Line-Side Device Only) Bit Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 RGA3 Receive Gain or Attenuation Incrementing the RXG3[3:0] ...
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Register 43. Line Current/Voltage Threshold Interrupt (Si3019 Line-Side Device Only) Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 CVT[7:0] Current/Voltage Threshold. Determines the threshold at which an interrupt is generated from either the LCS or ...
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Si3018/19/10 Register 45. Programmable Hybrid Register 1 Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB1[7:0] Programmable Hybrid Register 1. These bits are programmed with a coefficient value to adjust the hybrid response to reduce ...
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Register 47. Programmable Hybrid Register 3 Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB3[7:0] Programmable Hybrid Register 3. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end ...
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Si3018/19/10 Register 49. Programmable Hybrid Register 5 Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB5[7:0] Programmable Hybrid Register 5. These bits are programmed with a coefficient value to adjust the hybrid response to reduce ...
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Register 51. Programmable Hybrid Register 7 Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB7[7:0] Programmable Hybrid Register 7. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end ...
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Si3018/19/10 Register 59. Spark Quenching Control Bit Name TB3 SQ1 Type R/W R/W Reset settings = 0000_0000 Bit Name 7 TB3 For South Korea PTT compliance, set this bit, in addition to the RZ bit, to synthesize ...
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A —UL1950 3 PPENDIX RD Although designs using the Si3056 comply with the UL1950 3rd edition and pass all overcurrent and overvoltage tests, there are still several issues to consider. Figure 37 shows two designs that can pass the UL1950 ...
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Si3018/19/10 7. Pin Descriptions: Si3056 Pin # Pin Name 1 MCLK Master Clock Input. High speed master clock input. Generally supplied by the system crystal clock or modem/DSP. 2 FSYNC Frame Sync Output. Data framing signal that indicates the start ...
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Table 24. Si3056 Pin Descriptions (Continued) Pin # Pin Name 11 AOUT/INT Analog Speaker Out/Interrupt. Provides an analog output signal for driving a call progress speaker or a hardware interrupt for multiple sources of interrupts. 12 GND Ground. Connects to ...
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Si3018/19/10 8. Pin Descriptions: Si3018/19/10 Table 25. Si3018/19/10 Pin Descriptions Pin # Pin Name 1 QE Transistor Emitter. Connects to the emitter of Q3. 2 DCT DC Termination. Provides dc termination to the telephone network Receive Input. Serves ...
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Table 25. Si3018/19/10 Pin Descriptions (Continued) Pin # Pin Name 13 QB Transistor Base. Connects to the base of transistor Q4. 14 DCT3 DC Termination 3. Provides dc termination to the telephone network. 15 IGND Isolated Ground. Connects to ground ...
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Si3018/19/10 1,2 9. Ordering Guide Part Number Si3056-KS Si3056-X-FS Part Number Si3010-X-FS Si3018-X-FS Si3019-X-FS Notes: 1. "X" denotes product revision. 2. Add an "R" at the end of the device to denote tape and reel option; 2500 quantity per reel. ...
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Evaluation Board Ordering Guide Part Number Line-Side Device Si3056PPT-EVB Si3018 Parallel Port Si3056PPT1-EVB Si3019 Parallel Port Si3056PPT2-EVB Si3010 Parallel Port Si3056SSI-EVB Si3018 Serial Interface with Buffer Direct Connection to processor Si3056SSI1-EVB Si3019 Serial Interface with Buffer Si3056SSI2-EVB Si3010 Serial ...
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Si3018/19/10 11. Package Outline: 16-Pin SOIC Figure 38 illustrates the package details for the Si3056/18/19/10. Table 26 lists the values for the dimensions shown in the illustration aaa - Seating ...
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OCUMENT HANGE IST Revision 0.2 to Revision 0.71 Updated list of applications on cover page, including ability to support V.92 modems. Updated Transmit Full Scale Level test condition and note in Table 4 (AC Characteristics) for description ...
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Si3018/19/10 Revision 1.0 to Revision 1.01 Removed “Confidential” watermark. Revision 1.01 to Revision 1.02 Updated Table 2, “Loop Characteristics,” on page 6. Updated Table 4, “AC Characteristics,” on page 8 Updated "3.Bill of Materials" on page 19 Added optional caller ...
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S L ILICON ABORATORIES Application Note 13: Silicon DAA Software Guidelines Application Note 16: Multiple Device Support Application Note 17: Designing for International Safety Compliance Application Note 67: Layout Guidelines Application Note 72: Ring Detection/Validation with the Si305x DAAs Application ...
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