LMX2434EVAL National Semiconductor, LMX2434EVAL Datasheet

LMX2434EVAL

Manufacturer Part Number

LMX2434EVAL

Description

EVALUATION BOARD FOR LMX2434

Manufacturer

National Semiconductor

Series

PLLatinum™r

Datasheets

1.LMX2433SLEXNOPB.pdf (49 pages)

2.LMX2430EVAL.pdf (8 pages)

3.LMX2434EVAL.pdf (6 pages)

4.LMX2434EVAL.pdf (26 pages)

Specifications of LMX2434EVAL

Main Purpose

Timing, Frequency Synthesizer

Utilized Ic / Part

LMX2434

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Secondary Attributes

Embedded

Primary Attributes

Lead Free Status / Rohs Status

Not Compliant

Other names

*LMX2434EVAL

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Optimizing LMX243x Input

Sensitivity Using Simple

Matching Techniques

Abstract

The following note describes how maximum power can be

delivered from the Voltage Controlled Oscillator (VCO) out-

put to the FinRF input of a LMX243x frequency synthesizer

by means of performing a single element match.

Maximum power transfer is achieved by designing a match-

ing network that transforms the FinRF input (load) imped-

ance to an impedance that is equivalent to the VCO output

(source) impedance. In most applications, the VCO has an

output impedance equivalent to 50Ω. Furthermore, the trace

impedance of the Printed Circuit Board (PCB) is typically

designed to be 50Ω. This means that the matching network

should be designed to transform the FinRF input impedance

to 50Ω. Figure 1 demonstrates the principal of impedance

matching (transformation). The VCO output is represented

as a Thevenin equivalent of a voltage source and a 50Ω

series resistance.

A typical plot for the LMX243x UTCSP FinRF input imped-

ance is illustrated in Figure 2. The Smith Chart shows that for

frequencies less than 3400 MHz, the reactance is primarily

dominated by the capacitance from the PCB and CSP pack-

age. On the other hand, for frequencies greater than 3400

MHz, the reactance, for the most part, becomes dominated

by the internal lead inductance from the package bond wires.

It’s worth mentioning that the FinRF input impedance is very

dependent upon the type of package used.

Ideally, a perfect match is preferred everywhere within the

FinRF input’s range. This means that the matching network

designed should be able to ‘tune out’ the effects of the

package capacitance at the lower frequencies, as well as the

effects of the lead inductance at the higher frequencies. In

practice however, since the load is comprised of imaginary

elements, which are frequency dependent, the perfect match

can only occur at one frequency. Therefore, the matching

network is only optimized for a particular frequency. In the

case of PLLs, this corresponds to the VCO output frequency,

FinRF

FIGURE 1. Impedance Matching

AN200656

20065601

National Semiconductor

Application Note 1275

Ahmed Salem

May 2003

Evaluation Methodology

To keep the matching network simple and to demonstrate

that indeed an improvement in performance is achieved, a

single element match is used. In order to assess the im-

provement achieved, the device’s input sensitivity level is

determined before and after the matching network is in-

cluded. Therefore, an open loop sensitivity test is imple-

mented. The purpose of this test is to measure the accept-

able signal level to the FinRF input of the PLL. Outside the

acceptable signal range, the feedback divider begins to di-

vide incorrectly and miscount the frequency. Minimum sen-

sitivity is reached when the frequency error of the divided RF

input is greater than or equal to 1 Hz.

In most applications, the lower sensitivity limit is of concern

because it determines the minimum acceptable signal level

that is required to maintain lock. The objective of the match-

ing network, therefore, is to push the lower sensitivity limit

downwards. This means that at the particular frequency of

interest, i.e. the VCO output frequency, the matching net-

work should improve the FinRF input sensitivity.

Furthermore, a good match should also improve the fre-

quency response of the PLL. In most applications, it is

desirable to increase the upper frequency limit, i.e. push the

sensitivity curve further right. In most cases however, as

seen with the LMX243x UTCSP, this is difficult to achieve

due to internal circuit limitations.

To demonstrate the discussion above, several examples are

provided here.

FIGURE 2. LMX243x UTCSP FinRF Input Impedance

www.national.com

20065602

Related parts for LMX2434EVAL

LMX2434EVAL Summary of contents

Page 1

... Therefore, the matching network is only optimized for a particular frequency. In the case of PLLs, this corresponds to the VCO output frequency FinRF © 2003 National Semiconductor Corporation National Semiconductor Application Note 1275 Ahmed Salem May 2003 FIGURE 2. LMX243x UTCSP FinRF Input Impedance ...

Page 2

Optimizing Sensitivity at 5.0 GHz Suppose the requirement is to optimize the performance at 5.0 GHz for used in a particular 802.11a WLAN application. According to Figure 2, the FinRF input imped- ance lies on ...

Page 3

Optimizing Sensitivity at 6.0 GHz Now suppose the requirement is to optimize the perfor- mance at 6.0 GHz for used in a particluar cordless phone application. According to Figure 2, the FinRF input impedance again ...

Page 4

Optimizing Sensitivity at 2.0 GHz Now suppose the requirement is to optimize the perfor- mance at 2.0 GHz for used in a particular US TBQM handset application. Figure 2 now shows that the FinRF input ...

Page 5

LMX243x UTCSP FinRF Input Impedance Table Vcc = EN = 2.50V +25˚C A FinRF |Γ| (MHz) 100 0.86 200 0.86 300 0.85 400 0.84 500 0.83 600 0.82 700 0.82 800 0.81 900 0.80 1000 0.80 1100 0.79 ...

Page 6

... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...

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