SI5315-EVB Silicon Laboratories Inc, SI5315-EVB Datasheet - Page 35

• Manufacturer Part Number: SI5315-EVB
• Description: BOARD EVAL SI5315 8KHZ-644.53MHZ
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5315-EVB

• Main Purpose: Timing, Clock Multiplier
• Embedded: No
• Utilized Ic / Part: SI5315
• Primary Attributes: 2 Inputs, 2 Outputs
• Secondary Attributes: CML, CMOS, LVDS, LVPECL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Si5315
4.5. Holdover Mode
If an LOS condition exists on the selected input clock, the device enters holdover. In this mode, the device provides
a stable output frequency until the input clock returns and is validated. When the device enters holdover, the
internal oscillator is initially held to its last frequency value. Next, the internal oscillator slowly transitions to a
historical average frequency value that was taken over a time window of 6,711 ms in size that ended 26 ms before
the device entered holdover. This frequency value is taken from an internal memory location that keeps a record of
previous DSPLL frequency values. By using a historical average frequency, input clock phase and frequency
transients that may occur immediately preceding loss of clock or any event causing holdover do not affect the
holdover frequency. Also, noise related to input clock jitter or internal PLL jitter is minimized.
If a highly stable reference, such as an oven-controlled crystal oscillator, is supplied at XA/XB, an extremely stable
holdover can be achieved. If a crystal is supplied at the XA/XB port, the holdover stability will be limited by the
stability of the crystal; Table 3, “AC Characteristics” gives the specifications related to the holdover function.
4.5.1. Recovery from Holdover
When the input clock signal returns, the device transitions from holdover to the selected input clock. The device
performs hitless recovery from holdover. The clock transition from holdover to the returned input clock includes
"phase buildout" to absorb the phase difference between the holdover clock phase and the input clock phase. See
Table 3, “AC Characteristics” for specifications.
Rev. 0.26
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