LMK04000BEVALXO National Semiconductor, LMK04000BEVALXO Datasheet - Page 4

• Manufacturer Part Number: LMK04000BEVALXO
• Description: BOARD EVAL PREC CLOCK PLL XO
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LMK04000BEVALXO

• Main Purpose: Timing, Clock Conditioner
• Embedded: No
• Utilized Ic / Part: LMK04000
• Primary Attributes: 122.88 MHz Crystal
• Secondary Attributes: Integrated PLL & VCO
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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1.0 General Description ......................................................................................................................... 1
2.0 Features ........................................................................................................................................ 1
3.0 Target Applications .......................................................................................................................... 1
4.0 Functional Block Diagram ................................................................................................................. 3
5.0 Connection Diagram ........................................................................................................................ 6
6.0 Pin Descriptions ............................................................................................................................. 7
7.0 Absolute Maximum Ratings .............................................................................................................. 9
8.0 Package Thermal Resistance ............................................................................................................ 9
9.0 Recommended Operating Conditions ................................................................................................ 9
10.0 Electrical Characteristics ............................................................................................................... 10
11.0 Serial Data Timing Diagram .......................................................................................................... 22
12.0 Charge Pump Current Specification Definitions ................................................................................ 22
13.0 Typical Performance Characteristics .............................................................................................. 24
14.0 Features ..................................................................................................................................... 26
15.0 Functional Description .................................................................................................................. 27
16.0 General Programming Information ................................................................................................. 29
12.1 CHARGE PUMP OUTPUT CURRENT MAGNITUDE VARIATION VS. CHARGE PUMP OUTPUT
12.2 CHARGE PUMP SINK CURRENT VS. CHARGE PUMP OUTPUT SOURCE CURRENT
12.3 CHARGE PUMP OUTPUT CURRENT MAGNITUDE VARIATION VS. TEMPERATURE ................ 23
13.1 CLOCK OUTPUT AC CHARACTERISTICS ............................................................................. 24
14.1 SYSTEM ARCHITECTURE ................................................................................................... 26
14.2 REDUNDANT REFERENCE INPUTS (CLKin0/CLKin0*, CLKin1/CLKin1*) ................................... 26
14.3 PLL1 CLKinX (X=0,1) LOSS OF SIGNAL (LOS) ....................................................................... 26
14.4 INTEGRATED LOOP FILTER POLES ..................................................................................... 26
14.5 CLOCK DISTRIBUTION ....................................................................................................... 26
14.6 CLKout DIVIDE (CLKoutX_DIV, X = 0 to 4) .............................................................................. 26
14.7 CLKout DELAY (CLKoutX_DLY, X = 0 to 4) ............................................................................. 26
14.8 GLOBAL CLOCK OUTPUT SYNCHRONIZATION (SYNC*) ....................................................... 26
14.9 GLOBAL OUTPUT ENABLE AND LOCK DETECT .................................................................... 26
15.1 ARCHITECTURAL OVERVIEW .............................................................................................. 27
15.2 PHASE DETECTOR 1 (PD1) ................................................................................................. 27
15.3 PHASE DETECTOr 2 (PD2) .................................................................................................. 27
15.4 PLL2 FREQUENCY DOUBLER .............................................................................................. 27
15.5 INPUTS / OUTPUTS ............................................................................................................. 27
16.1 RECOMMENDED PROGRAMMING SEQUENCE .................................................................... 29
16.2 DEFAULT DEVICE REGISTER SETTINGS AFTER POWER ON/RESET .................................... 32
16.3 REGISTER R0 TO R4 ........................................................................................................... 33
16.4 REGISTERS 5, 6 .................................................................................................................. 34
16.5 REGISTER 7 ....................................................................................................................... 34
16.6 REGISTERS 8, 9 .................................................................................................................. 34
16.7 REGISTER 10 ..................................................................................................................... 34
16.8 REGISTER 11 ..................................................................................................................... 34
16.9 REGISTER 12 ..................................................................................................................... 35
VOLTAGE ................................................................................................................................ 23
MISMATCH .............................................................................................................................. 23
15.5.1 PLL1 Reference Inputs (CLKin0 / CLKin0*, CLKin1 / CLKin1*) .......................................... 27
15.5.2 PLL2 OSCin / OSCin* Port ........................................................................................... 27
15.5.3 CPout1 / CPout2 ........................................................................................................ 27
15.5.4 Fout .......................................................................................................................... 27
15.5.5 Digital Lock Detect 1 Bypass ........................................................................................ 28
15.5.6 Bias .......................................................................................................................... 28
16.3.1 CLKoutX_DIV: Clock Channel Divide Registers .............................................................. 33
16.3.2 EN_CLKoutX: Clock Channel Output Enable .................................................................. 33
16.3.3 CLKoutX_DLY: Clock Channel Phase Delay Adjustment .................................................. 33
16.3.4 CLKoutX/CLKoutX* LVCMOS Mode Control ................................................................... 33
16.3.5 CLKoutX/CLKoutX* LVPECL Mode Control .................................................................... 34
16.3.6 CLKoutX_MUX: Clock Output Mux ................................................................................ 34
16.5.1 RESET bit ................................................................................................................. 34
16.7.1 RC_DLD1_Start: PLL1 Digital Lock Detect Run Control bit ............................................... 34
16.8.1 CLKinX_BUFTYPE: PLL1 CLKinX/CLKinX* Buffer Mode Control ...................................... 34
16.8.2 CLKin_SEL: PLL1 Reference Clock Selection and Revertive Mode Control Bits .................. 35
16.8.3 CLKinX_LOS ............................................................................................................. 35
16.8.4 PLL1 Reference Clock LOS Timeout Control .................................................................. 35
16.8.5 LOS Output Type Control ............................................................................................ 35
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