SI5023-EVB Silicon Laboratories Inc, SI5023-EVB Datasheet - Page 27

• Manufacturer Part Number: SI5023-EVB
• Description: BOARD EVALUATION FOR SI5023
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5023-EVB

• Main Purpose: Timing, Clock and Data Recovery (CDR)
• Utilized Ic / Part: SI5023
• Processor To Be Evaluated: Si5023
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1134

Si5023
D
Revision 1.21 to Revision 1.22
Revision 1.22 to Revision 1.23
Revision 1.23 to Revision 1.24
27
OCUMENT
Updated "3. Typical Application Schematic" on page
11.
Updated Figure 11 on page 16.
Updated Table 9 on page 22.
Updated Table 2 on page 7.
Updated Table 3 on page 8.
Updated Table 9 on page 22.
Updated Figure 22, “28-Lead Quad Flat No-Lead
(QFN),” on page 26.
Updated Table 10, “Package Diagram Dimensions,”
on page 26.
Removed all references to Si5022.
Updated Table 2 on page 7.
Updated Tables 3 and 4 on page 8.
Updated Table 8 on page 13.
Updated "4.17. Voltage Regulator" on page 19.
Updated "6. Ordering Guide" on page 25.
(DOUT)” with updated values.
(CLKOUT)” with updated values.
Updated BERMON pin description.
Added “Output Common Mode Voltage (Si5023)
Added “Output Common Mode Voltage (Si5023)
Added “Output Clock Duty Cycle OC-48/12/3”
Changed “clock input” to “DIN inputs” for Loss-of-Signal.
Changed dimension A.
Changed dimension E2.
I
P
R
+V
+V
+V
Clarified f
Revised duty cycle, t
Revised slicing level accuracy
Removed OC3 support for 15/14 FEC
Due to removal of Si5022 references
Added “X” to part number.
dd
d
IN
ICM
OD
OCM
CLK
C
for the different settings of RATESEL
HANGE
CR-D
, C
TOL
L
IST
Rev. 1.3
Revision 1.24 to Revision 1.25
Revision 1.25 to Revision 1.3
Updated Table 2 on page 7.
Updated Table 3 on page 8.
Updated Table 4 on page 9.
Updated "4.8. Loss-of-Signal (LOS)" on page 13.
Updated "4.9. Bit Error Rate (BER) Detection" on
page 14.
Updated "4.10. Data Slicing Level" on page 14.
Updated pin description for RATESEL.
Added "7. Top Mark" on page 25.
Updated "8. Package Outline" on page 26.
Revised Figure 6, “LOS_LVL Mapping (PRBS23 Data),”
on page 14, showing internal noise limits.
Added limits for V
Updated V
Updated T
Updated T
Revised SLICE specification.
T
Added note describing valid signal.
Revised Figure 8.
Added Figures 9 and 10.
Added Figures 12 and 13.
Revised text.
AQ
min/max values updated.
OD
Cr-D
Cf-D
.
.
.
ICM
.