MAX19713EVCMODU+ Maxim Integrated Products, MAX19713EVCMODU+ Datasheet - Page 9

• Manufacturer Part Number: MAX19713EVCMODU+
• Description: EVAL MODULE FOR MAX19713
• Manufacturer: Maxim Integrated Products

Specifications of MAX19713EVCMODU+

• Main Purpose: Interface, Analog Front End (AFE)
• Embedded: No
• Utilized Ic / Part: MAX19713
• Primary Attributes: Dual 45MSPS 10-bit Rx ADCs & Tx DACs
• Secondary Attributes: Graphical User Interface, SPI™ & USB Interfaces
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX19710–MAX19713 feature two reference oper-
ation modes. The EV kits can be configured to use
either the internal (1.024V) reference or an external
user-supplied reference applied at the REFIN pad. The
AFEs generate the REFP and REFN voltages from the
selected reference voltage (refer to the MAX19710,
MAX19711, MAX19712, and MAX19713 data sheets for
more details). Measure the REFP and REFN voltages at
TP1 and TP2, respectively. Jumper JU2 controls the ref-
erence mode. See Table 2 for jumper configurations.
Table 2. Reference Shunt Settings (JU2)
* Default configuration.
Table 3. Digital Data Bit Locations
Note: Pins 1, 5, 7, 11, 13, 15, 17, and 39 of J2 are open. All other pins are connected to OGND.
SHUNT POSITION
Not installed
Installed*
CLKOUT
SIGNAL
BDOUT
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
_______________________________________________________________________________________
Internal reference mode.
External reference mode.
Apply an external reference voltage to
the REFIN pad.
DESCRIPTION
MAX19710–MAX19713 Evaluation
LOCATION
J2-37
J2-35
J2-33
J2-31
J2-29
J2-27
J2-25
J2-23
J2-21
J2-19
J3-19
J3-17
J3-15
J3-13
J3-11
J2-3
J2-9
J3-9
J3-7
J3-5
J3-3
J3-1
Reference
Kits/Evaluation Systems
The MAX19710–MAX19713 EV kits feature two 10-bit
parallel data buses used for full-duplex operation. The two
data buses are accessed on the EV kit through header
connectors J2 (Rx ADC bus) and J3 (Tx DAC bus).
Driver U2 buffers the digital outputs of the Rx ADC. This
driver is able to drive large capacitive loads, which may
be present at the logic analyzer connection. The out-
puts of the buffer are connected to a 40-pin header
(J2). The 20-pin header (J3) is used to connect to the
digital input of the Tx DAC. See Table 3 for bit locations
on headers J2 and J3.
The MAX19710–MAX19713 EV kits feature on-board
configurable buffers. By default, these buffers are config-
ured for unity gain. Measure the buffered voltage at the
BDAC1, BDAC2, and BDAC3 pads. Measure the
unbuffered voltage at the DAC1, DAC2, and DAC3 pads.
Configuring the Low-Speed DAC Buffers
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Digital Data Bit Locations
Digital Data Headers
Aux-ADC Digital Output
Incoming Clock Signal
(requires R38 short)
Data Bit 9 (MSB)
Data Bit 9 (MSB)
Data Bit 0 (LSB)
Data Bit 0 (LSB)
DESCRIPTION
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Data Bit 8
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Data Bit 8
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