DS3112DK Maxim Integrated Products, DS3112DK Datasheet - Page 95

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DS3112DK

Manufacturer Part Number
DS3112DK
Description
KIT DEMO FOR DS3112
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3112DK

Main Purpose
Interface, Crosspoint Switch/Multiplexer
Utilized Ic / Part
DS3112
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Transmit Packet End (TEND).
Bit 2: Transmit FIFO Low Watermark (TLWM).
Bit 4: Receive FIFO High Watermark (RHWM).
Bit 5: Receive Packet Start (RPS).
Bit 6: Receive Packet End (RPE).
Bit 7: Transmit FIFO Underrun (TUDR).
Bit 13: Receive FIFO Overrun (ROVR).
Bit 15: Receive Abort Sequence Detected (RABT).
0 = interrupt masked
1 = interrupt unmasked
0 = interrupt masked
1 = interrupt unmasked
0 = interrupt masked
1 = interrupt unmasked
0 = interrupt masked
1 = interrupt unmasked
0 = interrupt masked
1 = interrupt unmasked
0 = interrupt masked
1 = interrupt unmasked
0 = interrupt masked
1 = interrupt unmasked
0 = interrupt masked
1 = interrupt unmasked
TUDR
RABT
15
7
0
0
RPE
14
6
0
IHSR
Interrupt Mask for HDLC Status Register
88h
ROVR
RPS
13
5
0
0
RHWM
95 of 133
12
4
0
11
3
TLWM
10
2
0
1
9
TEND
DS3112
0
0
8

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