DS26303DK Maxim Integrated Products, DS26303DK Datasheet
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DS26303DK
Specifications of DS26303DK
Related parts for DS26303DK
DS26303DK Summary of contents
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... GENERAL DESCRIPTION The DS26303DK is a fully integrated design kit for the DS26303 3.3V, 8-port, E1/T1/J1 line interface unit (LIU). This design kit contains all the necessary circuitry to evaluate the DS26303 in all modes of operation. The design kit also includes an on-board microprocessor to run real-time code for further part evaluation ...
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... COMPONENT LIST .....................................................................................................................3 BOARD FLOORPLAN.................................................................................................................6 BASIC OPERATION....................................................................................................................7 HARDWARE CONFIGURATION ................................................................................................ UICK TART ARDWARE JTAG C ............................................................................................................................. 7 ONFIGURATION Table 1. JTAG Connector (J6) Pinout............................................................................................................... 7 Figure 1. DS26303DK JTAG Chain .................................................................................................................. DDRESS ATA US ONNECTOR Table 2. Address/Data Connector Pinout ......................................................................................................... ELECOM LOCK AND ATA Table 3. Telecom Connector Pinout ................................................................................................................. OARD IT RROR ATE Table 4. BERT Connector Pinout ..................................................................................................................... 9 ...
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COMPONENT LIST DESIGNATION QTY C1, C4, C6, C7, C18, C24, C26, C34, C36, C37, C38, C41, C43– 53 C47, C49, C50, C51, C53–C59, C61–C83, C85, C86, C90 C2, C3, C22, C30, C35, C40, C42, 13 C48, C52, C60, C84, C88, ...
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DESIGNATION QTY Resistors (0603) R1, R58, R87 3 DO NOT POPULATE R2, R14–R26, R28, R32–R43, R46– R50, R52, R54– R57, R63–R66, R68, R69, R71, 10kΩ ±5%, 1/16W resistors (0603) 57 R72, R73, R76, R77, R82, R85, R86, R88, R91, R93, ...
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DESIGNATION QTY PROM for FPGA U7 1 (44-pin TQFP) Dual RS-232 transmitter/receiver U8 1 (150-mil, 16-pin SO) U9, U12 2 High-speed buffers 1.5W, 3.3V or adj, 1A linear regulators U10, U18 2 (16-pin TSSOP-EP) U13, U15 2 Hex inverters (14-pin ...
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BOARD FLOORPLAN TCLK, RCLK, RLOS TPOS, RPOS, 5V TECLK CLK A TNEG, RNEG PWR JTAG USER SERIAL CON SWITCHES CON ON-BOARD µC RST BOARD USB Tx/Rx USB CON USER TCLK, RCLK, RLOS BNC TPOS, RPOS, TNEG, RNEG OSC OSC E1 ...
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... If using the USB port, connect a USB cable from DS26303DK (J3) to the PC. • Connect AC/DC adapter with an AC power source and the DS26303DK (J2). PWR LED should be on. JTAG Configuration The JTAG chain is controlled by the connector JTAG CON (J6) and two on-board switches: FLASH (SW3) and ONCE/JTAG (SW4) ...
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... JTDO Address/Data Bus Connector The DS26303DK has a connector (J1) to monitor all local bus activity for the design kit. All the signals can be captured with a high-impedance probe and displayed on an oscilloscope or logic analyzer. Note: If the FPGA switch (SW5 the “OFF” position, the on-board microcontroller will no longer drive any data onto the local bus. ...
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... Telecom Clock and Data Test Points The DS26303DK has high-impedance test points for all the telecom signals that are related to the LIU. These signals are split up by port number and marked with easy to read silkscreen labels. connector for port 1. The pinout for this connector is repeated for all 8 ports. ...
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... Most advanced microcontrollers have both a parallel interface and SPI interface such as the microcontroller on the DS26303DK. The command you send to the microcontroller through either the USB or serial port determines if that data is placed on the parallel or SPI bus. Refer to the data sheet for commands required to switch data ports ...
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Figure 3. SPI Configuration with PROM JTCLK JTMS JTDI JTDO Table 5. Configuration Memory D7 D6 ADDRESS CSB SCLK 0x00 1 0 0x01 0 0 0x02 0 1 0x03 0 0 0x04 0 1 0x05 0 0 0x06 0 1 ...
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... Start button on the Windows toolbar and select Programs -> ChipView -> ChipView. • Load the DS26303DK.def file. • Make sure that all the register settings are correct for the proper function desired for the DS26303DK. • Refer to the DS26303 data sheet for all questions pertaining to device functionality. MEMORY MAP The on-board microcontroller is configured to start the user address space at 0x81000000 ...
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... AREV: BOARD ASSEMBLY REVISION (Offset = 0X0006) AREV is read-only and displays the current assembly revision. PREV: FPGA REVISION (Offset = 0X0007) PREV is read-only and displays the current PLD firmware revision. CONTROL REGISTERS Register Name: CTRL_1 Register Description: DS26303DK FPGA CONTROL REGISTER 1 Register Offset: 0x08 Bit # 7 Name INT303 ENRLOS1 Bit 7: INT303 ...
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Register Name: ABSP Register Description: ADDRESS BANK SWAP POINTER Register Offset: 0x0A Bit # 7 6 Name D7 D6 Bits D0. These bits control the address bank for address 0x10 (TCLK N), 0x11 (TPOS), and ...
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Register Name: BTCLK Register Description: BERT TCLK SOURCE Register Offset: 0x0B Bit # 7 6 Name D7 D6 Bits D0. These bits control the source of the TCLK for the BERT. BTCLK 0x00 RCLK Port ...
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Register Name: BRCLK Register Description: BERT RCLK SOURCE Register Offset: 0x0C Bit # 7 6 Name D7 D6 Bits D0. These bits control the source of the RCLK for the BERT. BTCLK 0x00 RCLK Port ...
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Register Name: BRDAT Register Description: BERT RDAT SOURCE Register Offset: 0x0D Bit # 7 6 Name D7 D6 Bits D0. These bits control the source of the RDAT for the BERT. Note that the DS26303 ...
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Register Name: TCLK Register Description: PORT TCLK SOURCE Register Offset: 0x10 Bit # 7 6 Name D7 D6 Note: This is an indirect register that is related to ABSP (0x0A). See register description. Bits D0. ...
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Register Name: TPOS Register Description: PORT TPOS SOURCE Register Offset: 0x11 Bit # 7 6 Name D7 D6 Note: This is an indirect register that is related to ABSP (0x0A). See register description. Bits D0. ...
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Register Name: TNEG Register Description: PORT TNEG SOURCE Register Offset: 0x12 Bit # 7 6 Name D7 D6 Note: This is an indirect register that is related to ABSP (0x0A). See register description. Bits D0. ...
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... DS26303 INFORMATION For more information about the DS26303, refer to the DS26303 data sheet available on our website at www.maxim-ic.com/DS26303. DS26303DK INFORMATION For more information about the DS26303DK including software downloads www.maxim-ic.com/DS26303DK. TECHNICAL SUPPORT For additional technical support, e-mail your questions to telecom.support@dalsemi.com. SCHEMATICS The DS26303DK schematics are featured in the following 22 pages. ...
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