EVAL-AD7797EBZ Analog Devices Inc, EVAL-AD7797EBZ Datasheet - Page 11

• Manufacturer Part Number: EVAL-AD7797EBZ
• Description: BOARD EVALUATION FOR AD7797
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7797EBZ

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 123
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF/128
• Power (typ) @ Conditions: 1.6mW @ 123SPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7797
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ON-CHIP REGISTERS
The ADC is controlled and configured via a number of on-chip
registers, which are described on the following pages. In the
following descriptions, set implies a Logic 1 State and cleared
implies a Logic 0 State, unless otherwise stated.
COMMUNICATION REGISTER
RS2, RS1, RS0 = 0, 0, 0
The communication register is an 8-bit write-only register. All
communication to the part must start with a write operation to
this register. The data written to the communication register
determines whether the next operation is a read or write opera-
tion, and selects the register where this operation takes place.
MSB
CR7
WEN(0)
Table 9. Communication Register Bit Designations
Bit Location
CR7
CR6
CR5 to CR3
CR2
CR1 to CR0
Table 10. Register Selection
RS2
0
0
0
0
0
1
1
1
1
RS1
0
0
0
1
1
0
0
1
1
Bit Name
WEN
R/W
RS2 to RS0
CREAD
0
CR6
R/W(0)
RS0
0
0
1
0
1
0
1
0
1
Register
Communication Register During a Write Operation
Status Register During a Read Operation
Mode Register
Configuration Register
Data Register
ID Register
Reserved
Offset Register
Full-Scale Register
Description
Write Enable Bit. A 0 must be written to this bit first to ensure that a write to the communication register
occurs. If a 1 is the first bit written, the part does not clock onto subsequent bits in the register; it stays at this
bit location until a 0 is written. Once a 0 is written to the WEN bit, the next seven bits are loaded to the
communication register.
A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position
indicates that the next operation is a read from the designated register.
Register Address Bits. These address bits determine which ADC registers are being selected during this serial
interface communication. See Table 10.
Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial
interface is configured to continuously read the data register. For example, the contents of the data register are
automatically placed on the DOUT pin when the SCLK pulses are applied and after the RDY pin goes low. This
indicates that a conversion is complete. The communication register does not have to be written to for data reads.
To enable continuous read mode, the instruction 01011100 must be written to the communication register.
To exit the continuous read mode, the instruction 01011000 must be written to the communication register
while the RDY pin is low. While in continuous read mode, the ADC monitors activity on the DIN line so it can
receive the instruction to exit continuous read mode. Additionally, a reset occurs if 32 consecutive 1s are seen
on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is written to the device.
These bits must be programmed to Logic 0 for correct operation.
CR5
RS2(0)
CR4
RS1(0)
Rev. A | Page 11 of 24
CR3
RS0(0)
Once the subsequent read or write operation to the selected
register is complete, the interface returns to where it expects a
write operation to the communication register (this is the
default state of the interface). On power-up or after a reset, the
ADC is in this default state waiting for a write operation to the
communication register. In situations where the interface
sequence is lost, a write operation of at least 32 serial clock
cycles with DIN high returns the ADC to this default state by
resetting the entire part. Table 9 outlines the bit designations for
the communication register. CR0 through CR7 indicate the bit
location, with CR denoting that the bits are in the communication
register. CR7 denotes the first bit of the data stream. The number
in brackets indicates the power-on/reset default status of that bit.
CR2
CREAD(0)
Register Size
8 bits
8 bits
16 bits
16 bits
16 bits (AD7796), 24 bits (AD7797)
8 bits
8 bits
16 bits (AD7796), 24 bits (AD7797)
16 bits (AD7796), 24 bits (AD7797)
CR1
0(0)
AD7796/AD7797
LSB
CR0
0(0)