EVAL-AD7796EBZ Analog Devices Inc, EVAL-AD7796EBZ Datasheet - Page 16
![no-image](/images/manufacturer_photos/0/0/57/analog_devices_inc_sml.jpg)
EVAL-AD7796EBZ
Manufacturer Part Number
EVAL-AD7796EBZ
Description
BOARD EVALUATION FOR AD7796
Manufacturer
Analog Devices Inc
Specifications of EVAL-AD7796EBZ
Number Of Adc's
1
Number Of Bits
16
Sampling Rate (per Second)
123
Data Interface
Serial
Inputs Per Adc
1 Differential
Input Range
±VREF/128
Power (typ) @ Conditions
1.6mW @ 123SPS
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
AD7796
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD7796/AD7797
ADC CIRCUIT INFORMATION
OVERVIEW
The AD7796/AD7797 are low power ADCs that incorporate a
Σ-Δ modulator, in-amp, and an on-chip digital filter intended
for measuring wide dynamic range, low frequency signals, such
as those in pressure transducers and weigh scales.
Each part has one differential input that is buffered. Figure 10
shows the basic connections required to operate the part.
OUT–
The output rate of the AD7796/AD7797 (f
programmable. The allowable update rates, along with the
corresponding settling times, are listed in Table 14. Normal
mode rejection is the major function of the digital filter.
Simultaneous 50 Hz and 60 Hz rejection is optimized when the
update rate equals 16.7 Hz or less because notches are placed at
both 50 Hz and 60 Hz with these update rates (see Figure 12).
The AD7796/AD7797 use slightly different filter types,
depending on the output update rate used to optimize the
rejection of quantization noise and device noise. When the
update rate is 4.17 Hz to 12.5 Hz, a Sinc
filter are used. When the update rate is 16.7 Hz to 33.2 Hz,
a modified Sinc
50 Hz/60 Hz rejection when the update rate equals 16.7 Hz.
A Sinc
123 Hz. Figure 11 to Figure 13 show the frequency response of
the different filter types for some of the update rates.
IN+
IN–
V
4
DD
filter is used when the update rate is from 50 Hz to
OUT+
AIN(+)
AIN(–)
REFIN(+)
REFIN(–)
3
Figure 10. Basic Connection Diagram
filter is used. This filter gives simultaneous
SENSOR
TEMP
MUX
AV
GND
DD
GND
V
DD
×128
ADC
AD7796/AD7797
Σ-Δ
3
filter and an averaging
ADC
INTERFACE
INTERNAL
CONTROL
CLOCK
SERIAL
LOGIC
) is user-
AND
CLK
DOUT/RDY
DIN
SCLK
CS
DV
DD
Rev. A | Page 16 of 24
–100
–100
–100
–20
–40
–60
–80
–20
–40
–60
–80
–20
–40
–60
–80
0
0
0
0
0
0
Figure 11. Filter Profile with Update Rate = 4.17 Hz
Figure 12. Filter Profile with Update Rate = 16.7 Hz
Figure 13. Filter Profile with Update Rate = 50 Hz
100
20
20
200
40
300
60
40
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
400
80
500
100
60
600
120
80
700
140
800
160
100
900
180
1000
1
2
20
00