EVAL-AD7864-3CB Analog Devices Inc, EVAL-AD7864-3CB Datasheet - Page 15

• Manufacturer Part Number: EVAL-AD7864-3CB
• Description: BOARD EVAL FOR AD7864-3
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7864-3CB

• Rohs Status: RoHS non-compliant
• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 520k
• Data Interface: Parallel
• Inputs Per Adc: 4 Differential
• Input Range: ±2.5 V
• Power (typ) @ Conditions: 90mW @ 520kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7864-3

SELECTING A CONVERSION SEQUENCE
Any subset of the four channels, V
conversion. The selected channels are converted in ascending
order. For example, if the channel selection includes V
and V
The conversion sequence selection can be made either by using
the hardware channel select input pins (SL1 through SL4) or by
programming the channel select register. A logic high on a
hardware channel select pin (or Logic 1 in the channel select
register) when CONVST goes logic high marks the associated
analog input channel for inclusion in the conversion sequence.
Figure 7 shows the arrangement used. The H/S SEL controls a
multiplexer that selects the source of the conversion sequence
information, that is, from the hardware channel select pins (SL1
to SL4) or from the channel selection register. When a conver-
sion begins, the output from the multiplexer is latched until the
end of the conversion sequence. The data bus bits, DB0 to DB3,
(DB0 representing Channel 1 through DB3 representing Channel 4)
are bidirectional and become inputs to the channel select register
when RD is logic high and CS and WR are logic low. The logic
state on DB0 to DB3 is latched into the channel select register
when WR goes logic high.
D3
D2
DATA BUS
WR
CS
D1
IN3
DATA
, the conversion sequence is V
D0
WR
RD
CS
HARDWARE CHANNEL
SELECT PINS
Figure 8. Channel Selection via Software Control
CHANNEL SELECT
Figure 7. Channel Select Inputs and Registers
REGISTER
t
14
SL1
SL2
SL3
SL4
WR
H/S SEL
t
t
16
13
DATA IN
TRANSPARENT WHILE WAITING FOR
CONVST. LATCHED ON THE RISING
EDGE OF CONVST AND DURING A
CONVERSION SEQUENCE.
t
IN1
15
t
17
to V
LATCH
IN1
, V
IN4
IN3
, can be selected for
, and then V
SELECT INDIVIDUAL
TRACK-AND-HOLDS
FOR CONVERSION
SEQUENCER
IN4
, V
IN4
IN1
Rev. D | Page 15 of 28
.
,
TIMING AND CONTROL
Reading Between Each Conversion in the Conversion
Sequence
Figure 9 shows the timing and control sequence required to
obtain the optimum throughput rate from the AD7864. To
obtain the optimum throughput from the AD7864, the user
must read the result of each conversion as it becomes available.
The timing diagram in Figure 9 shows a read operation each
time the EOC signal goes logic low. The timing in
shows a conversion on all four analog channels (SL1 to SL4 = 1,
see the
four
each of the four conversions.
A conversion is initiated on the rising edge of CONVST. This
places all four track-and-holds into hold simultaneously. New
data from this conversion sequence is available for the first
channel selected (V
subsequent channel is completed at 1.65 μs intervals. The end of
each conversion is indicated by the falling edge of the EOC
signal. The BUSY output signal indicates the end-of-conversion
for all selected channels (four in this case).
Data is read from the part via a 12-bit parallel data bus with
standard CS and RD signals. The CS and RD inputs are
internally gated to enable the conversion result onto the data
bus. The data lines (DB0 to DB11) leave their high impedance
state when both CS and RD are logic low. Therefore, CS can be
permanently tied logic low and the RD signal used to access the
conversion result. Because each conversion result is latched into
its output data register prior to EOC going logic low, another
option is to tie the EOC and RD pins together and use the rising
edge of EOC to latch the conversion result. Although the
AD7864 has some special features that permit reading during a
conversion (such as a separate supply for the output data
drivers, V
that the read operation be completed when EOC is logic low, that
is, before the start of the next conversion. Although
shows the read operation occurring during the
read operation can occur at any time.
specification referred to as the quiet time. Quiet time is the
amount of time that should be left after a read operation and
before the next conversion is initiated. The quiet time depends
heavily on data bus capacitance, but 50 ns to 100 ns is typical.
The signal labeled FRSTDATA (first data-word) indicates to the
user that the pointer associated with the output data registers is
pointing to the first conversion result by going logic high. The
pointer is reset to point to the first data location (that is, the first
conversion result,) at the end of the first conversion (FRSTDATA
EOC pulses and four read operations to access the result of
Selecting a Conversion Sequence
DRIVE
) for optimum performance it is recommended
IN1
) 1.65 μs later. The conversion on each
Figure 10
section), thus there are
EOC pulse, a
shows a timing
Figure 9
Figure 10
AD7864