ADC101S101EVAL National Semiconductor, ADC101S101EVAL Datasheet - Page 13

• Manufacturer Part Number: ADC101S101EVAL
• Description: BOARD EVALUATION FOR ADC101S101
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC101S101EVAL

• Number Of Adc's: 1
• Number Of Bits: 10
• Sampling Rate (per Second): 1M
• Data Interface: Serial
• Inputs Per Adc: 1 Single Ended
• Input Range: 0 ~ 5.25 V
• Power (typ) @ Conditions: 10mW @ 1MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC101S101
• Lead Free Status / RoHS Status: Not applicable / Not applicable

5.0 ANALOG INPUTS
An equivalent circuit for one of the ADC's input channels is
shown in
for the analog inputs. At no time should any input go beyond
(V
begin conducting, which could result in erratic operation. For
this reason, the ESD diodes should not be used to clamp the
input signal.
The capacitor C1 in
is mainly the package pin capacitance. Resistor R1 is the on
resistance of the multiplexer and track / hold switch, and is
typically 500Ω. Capacitor C2 is the ADC sampling capacitor
and is typically 26 pF. The ADC will deliver best performance
when driven by a low-impedance source to eliminate distor-
tion caused by the charging of the sampling capacitance. This
is especially important when using the ADC to sample AC
signals. Also important when sampling dynamic signals is an
anti-aliasing filter.
6.0 DIGITAL INPUTS AND OUTPUTS
The ADC digital inputs (SCLK and CS) are not limited by the
same absolute maximum ratings as the analog inputs. The
digital input pins are instead limited to +5.25V with respect to
GND, regardless of V
ADC to be interfaced with a wide range of logic levels, inde-
pendent of the supply voltage.
7.0 MODES OF OPERATION
The ADC has two possible modes of operation: normal mode,
and shutdown mode. The ADC enters normal mode (and a
A
+ 300 mV) or (GND − 300 mV), as these ESD diodes will
Figure
FIGURE 7. Equivalent Input Circuit
7. Diodes D1 and D2 provide ESD protection
Figure 7
A
, the supply voltage. This allows the
has a typical value of 4 pF, and
FIGURE 6. Typical Application Circuit
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conversion process is begun) when CS is pulled low. The de-
vice will enter shutdown mode if CS is pulled high before the
tenth falling edge of SCLK after CS is pulled low, or will stay
in normal mode if CS remains low. Once in shutdown mode,
the device will stay there until CS is brought low again. By
varying the ratio of time spent in the normal and shutdown
modes, a system may trade-off throughput for power con-
sumption, with a sample rate as low as zero.
7.1 Normal Mode
The fastest possible throughput is obtained by leaving the
ADC in normal mode at all times, so there are no power-up
delays. To keep the device in normal mode continuously,
CS must be kept low until after the 10th falling edge of SCLK
after the start of a conversion (remember that a conversion is
initiated by bringing CS low).
If CS is brought high after the 10th falling edge, but before the
16th falling edge, the device will remain in normal mode, but
the current conversion will be aborted, and SDATA will return
to TRI-STATE (truncating the output word).
Sixteen SCLK cycles are required to read all of a conversion
word from the device. After sixteen SCLK cycles have
elapsed, CS may be idled either high or low until the next
conversion. If CS is idled low, it must be brought high again
before the start of the next conversion, which begins when
CS is again brought low.
After sixteen SCLK cycles, SDATA returns to TRI-STATE.
Another conversion may be started, after t
by bringing CS low again.
7.2 Shutdown Mode
Shutdown mode is appropriate for applications that either do
not sample continuously, or it is acceptable to trade through-
put for power consumption. When the ADC is in shutdown
mode, all of the analog circuitry is turned off.
To enter shutdown mode, a conversion must be interrupted
by bringing CS back high anytime between the second and
tenth falling edges of SCLK, as shown in Figure 8. Once CS
has been brought high in this manner, the device will enter
shutdown mode; the current conversion will be aborted and
SDATA will enter TRI-STATE. If CS is brought high before the
second falling edge of SCLK, the device will not change
mode; this is to avoid accidentally changing mode as a result
of noise on the CS line.
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