ADC108S022EVAL/NOPB National Semiconductor, ADC108S022EVAL/NOPB Datasheet - Page 15

• Manufacturer Part Number: ADC108S022EVAL/NOPB
• Description: BOARD EVALUATION FOR ADC108S022
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC108S022EVAL/NOPB

• Number Of Adc's: 1
• Number Of Bits: 10
• Sampling Rate (per Second): 200k
• Data Interface: SPI™, QSPI™, MICROWIRE™, and DSP
• Inputs Per Adc: 8 Single Ended
• Input Range: 4.9 Vpp
• Power (typ) @ Conditions: 6.4mW @ 200kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Utilized Ic / Part: ADC108S022
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC108S022EVAL

The capacitor C1 in
is mainly the package pin capacitance. Resistor R1 is the on
resistance of the multiplexer and track / hold switch and is
typically 500 ohms. Capacitor C2 is the ADC108S022 sam-
pling capacitor, and is typically 30 pF. The ADC108S022 will
deliver best performance when driven by a low-impedance
source (less than 100 ohms). This is especially important
when using the ADC108S022 to sample dynamic signals. Al-
so important when sampling dynamic signals is a band-pass
or low-pass filter which reduces harmonics and noise in the
input. These filters are often referred to as anti-aliasing filters.
1.5 DIGITAL INPUTS AND OUTPUTS
The ADC108S022's digital inputs (SCLK, CS, and DIN) have
an operating range of 0V to V
2.2 POWER SUPPLY CONSIDERATIONS
There are three major power supply concerns with this prod-
uct: power supply sequencing, power management, and the
effect of digital supply noise on the analog supply.
2.2.1 Power Supply Sequence
The ADC108S022 is a dual-supply device. The two supply
pins share ESD resources, so care must be exercised to en-
sure that the power is applied in the correct sequence. To
avoid turning on the ESD diodes, the digital supply (V
not exceed the analog supply (V
even on a transient basis. Therefore, V
or concurrently with V
2.2.2 Power Management
The ADC108S022 is fully powered-up whenever CS is low
and fully powered-down whenever CS is high, with one ex-
FIGURE 7. Equivalent Input Circuit
Figure 7
D
.
has a typical value of 3 pF and
A
. They are not prone to latch-
A
) by more than 300 mV, not
A
must ramp up before
FIGURE 8. Typical Application Circuit
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D
) can-
15
up and may be asserted before the digital supply (V
any risk. The digital output (DOUT) operating range is con-
trolled by V
the output low voltage is 0.4V (max).
2.0 Applications Information
2.1 TYPICAL APPLICATION CIRCUIT
A typical application is shown in
digital supply pins are both powered in this example by the
National LP2950 low-dropout voltage regulator. The analog
supply is bypassed with a capacitor network located close to
the ADC108S022. The digital supply is separated from the
analog supply by an isolation resistor and bypassed with ad-
ditional capacitors. The ADC108S022 uses the analog supply
(V
kept as clean as possible. Due to the low power requirements
of the ADC108S022, it is also possible to use a precision ref-
erence as a power supply.
To minimize the error caused by the changing input capaci-
tance of the ADC108S022, a capacitor is connected from
each input pin to ground. The capacitor, which is much larger
than the input capacitance of the ADC108S022 when in track
mode, provides the current to quickly charge the sampling
capacitor of the ADC108S022. An isolation resistor is added
to isolate the load capacitance from the input source.
ception. If operating in continuous conversion mode, the AD-
C108S022 automatically enters power-down mode between
SCLK's 16th falling edge of a conversion and SCLK's 1st
falling edge of the subsequent conversion (see
In continuous conversion mode, the ADC108S022 can per-
form multiple conversions back to back. Each conversion
requires 16 SCLK cycles and the ADC108S022 will perform
conversions continuously as long as CS is held low. Contin-
uous mode offers maximum throughput.
In burst mode, the user may trade off throughput for power
consumption by performing fewer conversions per unit time.
This means spending more time in power-down mode and
less time in normal mode. By utilizing this technique, the user
can achieve very low sample rates while still utilizing an SCLK
frequency within the electrical specifications. The Power Con-
sumption vs. SCLK curve in the Typical Performance Curves
A
) as its reference voltage, so it is very important that V
D
. The output high voltage is V
Figure
8. The split analog and
D
- 0.5V (min) while
20164513
Figure
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D
) without
1).
A
be