ADC11C125LFEB/NOPB National Semiconductor, ADC11C125LFEB/NOPB Datasheet - Page 20

• Manufacturer Part Number: ADC11C125LFEB/NOPB
• Description: BOARD EVAL ADC11C125
• Manufacturer: National Semiconductor

Specifications of ADC11C125LFEB/NOPB

• Number Of Adc's: 1
• Number Of Bits: 11
• Sampling Rate (per Second): 125M
• Inputs Per Adc: 1 Differential
• Power (typ) @ Conditions: 608mW @ 125MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC11C125
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC11C125LFEB

www.national.com
4.0 DIGITAL OUTPUTS
Digital outputs consist of the 1.8V CMOS signals D0-D10,
DRDY, OVR and OGND.
The ADC11C125 has 16 CMOS compatible data output pins:
11 data output bits corresponding to the converted input val-
ue, a data ready (DRDY) signal that should be used to capture
the output data, an over-range indicator (OVR) which is set
high when the sample amplitude exceeds the 11-Bit conver-
sion range and three output ground pins (OGND) which
should be ignored except when used for compatibility with a
12 or 14 bit part. Valid data is present at these outputs while
the PD/Sleep pin is low.
Data should be captured and latched with the rising edge of
the DRDY signal. Depending on the setup and hold time re-
quirements of the receiving circuit (ASIC), either the rising
edge or the falling edge of the DRDY signal can be used to
latch the data. Generally, rising-edge capture would maxi-
mize setup time with minimal hold time; while falling-edge-
capture would maximize hold time with minimal setup time.
However, actual timing for the falling-edge case depends
greatly on the CLK frequency and both cases also depend on
the delays inside the ASIC. Refer to the AC Electrical Char-
acterisitics table.
Be very careful when driving a high capacitance bus. The
more capacitance the output drivers must charge for each
20
conversion, the more instantaneous digital current flows
through V
spikes can cause on-chip ground noise and couple into the
analog circuitry, degrading dynamic performance. Adequate
bypassing, limiting output capacitance and careful attention
to the ground plane will reduce this problem. Additionally, bus
capacitance beyond the specified 5 pF/pin will cause t
increase, reducing the setup and hold time of the ADC output
data. The result could be an apparent reduction in dynamic
performance.
To minimize noise due to output switching, the load currents
at the digital outputs should be minimized. This can be done
by using a programmable logic device (PLD) such as the
LC4032V-25TN48C to level translate the ADC output data
from 1.8V to 3.3V for use by any other circuitry. Only one load
should be connected to each output pin. The outputs of the
ADC14155 have 40Ω on-chip series resistors to limit the out-
put currents at the digital outputs. Additionally, inserting se-
ries resistors of about 22Ω at the digital outputs, close to the
ADC pins, will isolate the outputs from trace and other circuit
capacitances and limit the output currents, which could oth-
erwise result in performance degradation. See Figure 4.
DR
and DRGND. These large charging current
OD
to