ADC12C170LFEB/NOPB National Semiconductor, ADC12C170LFEB/NOPB Datasheet - Page 22

• Manufacturer Part Number: ADC12C170LFEB/NOPB
• Description: BOARD EVAL ADC12C170LF
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC12C170LFEB/NOPB

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 170M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Power (typ) @ Conditions: 715mW @ 170MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC12C170
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC12C170LFEB

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5.0 POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 0.1 µF ca-
pacitor and with a 0.01 µF ceramic chip capacitor close to
each power pin. Leadless chip capacitors are preferred be-
cause they have low series inductance.
As is the case with all high-speed converters, the AD-
C12C170 is sensitive to power supply noise. Accordingly, the
noise on the analog supply pin should be kept below 100
mV
No pin should ever have a voltage on it that is in excess of the
supply voltages, not even on a transient basis. Be especially
careful of this during power turn on and turn off.
The V
operated from a supply in the range of 1.6V to 2.0V. This en-
ables lower power operation, reduces the noise coupling
effects from the digital outputs to the analog circuitry and sim-
plifies interfacing to lower voltage devices and systems. Note,
however, that t
lator may be required to interface the digital output signals of
the ADC12C170 to non-1.8V CMOS devices.
6.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essen-
tial to ensure accurate conversion. Maintaining separate ana-
log and digital areas of the board, with the ADC12C170
between these areas, is required to achieve specified perfor-
mance.
The ground return for the data outputs (DRGND) carries the
ground current for the output drivers. The output current can
exhibit high transients that could add noise to the conversion
process. To prevent this from happening, the DRGND pins
should NOT be connected to system ground in close proximity
to any of the ADC12C170's other ground pins.
Capacitive coupling between the typically noisy digital circuit-
ry and the sensitive analog circuitry can lead to poor perfor-
mance. The solution is to keep the analog circuitry separated
from the digital circuitry, and to keep the clock line as short as
possible.
The effects of the noise generated from the ADC output
switching can be minimized through the use of 22Ω resistors
in series with each data output line. Locate these resistors as
close to the ADC output pins as possible.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane area.
Generally, analog and digital lines should cross each other at
90° to avoid crosstalk. To maximize accuracy in high speed,
high resolution systems, however, avoid crossing analog and
digital lines altogether. It is important to keep clock lines as
short as possible and isolated from ALL other lines, including
other digital lines. Even the generally accepted 90° crossing
should be avoided with the clock line as even a little coupling
can cause problems at high frequencies. This is because oth-
er lines can introduce jitter into the clock line, which can lead
to degradation of SNR. Also, the high speed clock can intro-
duce noise into the analog chain.
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
P-P
DR
.
pin provides power for the output drivers and may be
OD
increases with reduced V
DR
. A level trans-
22
through all components should form a straight line wherever
possible.
Be especially careful with the layout of inductors and trans-
formers. Mutual inductance can change the characteristics of
the circuit in which they are used. Inductors and transformers
should not be placed side by side, even with just a small part
of their bodies beside each other. For instance, place trans-
formers for the analog input and the clock input at 90° to one
another to avoid magnetic coupling.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any ex-
ternal component (e.g., a filter capacitor) connected between
the converter's input pins and ground or to the reference input
pin and ground should be connected to a very clean point in
the ground plane.
All analog circuitry (input amplifiers, filters, reference compo-
nents, etc.) should be placed in the analog area of the board.
All digital circuitry and dynamic I/O lines should be placed in
the digital area of the board. The ADC12C170 should be be-
tween these two areas. Furthermore, all components in the
reference circuitry and the input signal chain that are con-
nected to ground should be connected together with short
traces and enter the ground plane at a single, quiet point. All
ground connections should have a low inductance path to
ground.
7.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source
driving the CLK input must have a sharp transition region and
be free of jitter. Isolate the ADC clock from any digital circuitry
with buffers, as with the clock tree shown in Figure 5 . The
gates used in the clock tree must be capable of operating at
frequencies much higher than those used if added jitter is to
be prevented. Best performance will be obtained with a sin-
gle-ended drive input drive, compared with a differential clock.
As mentioned in Section 6.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
from any other signals. Other signals can introduce jitter into
the clock signal, which can lead to reduced SNR perfor-
mance, and the clock can introduce noise into other lines.
Even lines with 90° crossings have capacitive coupling, so try
to avoid even these 90° crossings of the clock line.
FIGURE 5. Isolating the ADC Clock from other Circuitry
with a Clock Tree
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