ADC14DS105KARB/NOPB National Semiconductor, ADC14DS105KARB/NOPB Datasheet - Page 22

• Manufacturer Part Number: ADC14DS105KARB/NOPB
• Description: BOARD EVAL FOR ADC14DS105KARB
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC14DS105KARB/NOPB

• Design Resources: ADC14DS105KARB Ref Design
• Number Of Adc's: 2
• Number Of Bits: 14
• Sampling Rate (per Second): 105M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Power (typ) @ Conditions: 1W @ 105MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC14DS105
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC14DS105KARB

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3.8 SCSb, SDI, SCLK
These pins are part of the SPI interface. See Section 5.0 for
more information.
4.0 DIGITAL OUTPUTS
Digital outputs consist of six LVDS signal pairs (SD0_A,
SD1_A, SD0_B, SD1_B, OUTCLK, FRAME) and CMOS logic
outputs ORA, ORB, DLL_Lock, and SDO.
4.1 LVDS Outputs
The digital data for each channel is provided in a serial format.
Two modes of operation are available for the serial data for-
mat. Single-lane serial format (shown in Figure 2) uses one
set of differential data signals per channel. Dual-lane serial
format (shown in Figure 3) uses two sets of differential data
signals per channel in order to slow down the data and clock
frequency by a factor of 2. At slower rates of operation (typi-
cally below 65 MSPS) the single-lane mode may the most
efficient to use. At higher rates the user may want to employ
5.0 Serial Control Interface
The ADC14DS105 has a serial interface that allows access
to the control registers. The serial interface is a generic 4-wire
synchronous interface that is compatible with SPI type inter-
faces that are used on many microcontrollers and DSP con-
trollers.
The ADC's input clock must be running for the Serial Control
Interface to operate. It is enabled when the SPI_EN (pin 56)
signal is asserted high. In this case the direct control pins (OF/
FIGURE 9. Application Circuit
22
the dual-lane scheme. In either case DDR-type clocking is
used. For each data channel, an overrange indication is also
provided. The OR signal is updated with each frame of data.
4.2 ORA, ORB
These CMOS outputs are asserted logic-high when their re-
spective channel’s data output is out-of-range in either high
or low direction.
4.3 DLL_Lock
When the internal DLL is locked to the input CLK, this pin
outputs a logic high. If the input CLK is changed abruptly, the
internal DLL may become unlocked and this pin will output a
logic low. Cycle Reset_DLL to re-lock the DLL to the input
CLK.
4.4 SDO
This pin is part of the SPI interface. See Section 5.0 for more
information.
DCS, PD_A, PD_B, DLC, WAM, TEST) have no effect. When
this signal is deasserted, the SPI interface is disabled and the
direct control pins are enabled.
Each serial interface access cycle is exactly 16 bits long. Fig-
ure 10 shows the access protocol used by this interface. Each
signal's function is described below. The Read Timing is
shown in Figure 11, while the Write Timing is shown in Figure
12
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