MAX105EVKIT Maxim Integrated Products, MAX105EVKIT Datasheet - Page 3

• Manufacturer Part Number: MAX105EVKIT
• Description: KIT EVAL FOR MAX105 AND MAX107
• Manufacturer: Maxim Integrated Products

Specifications of MAX105EVKIT

• Number Of Adc's: 2
• Number Of Bits: 6
• Sampling Rate (per Second): 800M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 800 mVpp
• Power (typ) @ Conditions: 2.6W @ 800MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MAX105, MAX107
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1. LVDS Outputs and Functional Description
The MAX105 EV kit requires separate analog and digi-
tal power supplies for best performance. A +3.3V ±10%
power supply is used to power the digital portion
(OVCC) of the ADC. A separate +5.0V ±5% power sup-
ply is used to power the analog portion (AVCC) of the
ADC. Ferrite beads are used to filter out high-frequency
noise at the analog power supply. At 100MHz, the fer-
rite beads have an impedance of 600Ω.
The clock signals CLK± are AC-coupled from the SMA
connectors J3 and J4. The DC-biasing level is internally
set to the reference voltage. The MAX105’s clock input
resistance is 5kΩ. However, the EV kit’s clock input
resistance is set by an external resistor to 50Ω. An AC-
coupled, differential sine-wave signal may be applied
to the CLK± SMA connectors (Figure 3). The signal
must not exceed a magnitude of 1.4V
clock frequency should be 800MHz for MAX105
P5I+, P5I- (MSB)
P4I+, P4I-
P3I+, P3I-
P2I+, P2I-
P1I+, P1I-
P0I+, P0I- (LSB)
A5I+, A5I- (MSB)
A4I+, A4I-
A3I+, A3I-
A2I+, A2I-
A1I+, A1I-
A0I+, A0I- (LSB)
P5Q+, P5Q- (MSB)
P4Q+, P4Q-
P3Q+, P3Q-
P2Q+, P2Q-
P1Q+, P1Q-
P0Q+, P0Q- (LSB)
A5Q+, A5Q- (MSB)
A4Q+, A4Q-
A3Q+, A3Q-
A2Q+, A2Q-
A1Q+, A1Q-
A0Q+, A0Q- (LSB)
DOR+, DOR-
DREADY+,
DREADY-
LVDS OUTPUT
SIGNALS
_______________________________________________________________________________________
EV KIT HEADER
LOCATION
JU52, JU53
JU48, JU49
JU44, JU45
JU12, JU13
JU40, JU41
JU36, JU37
JU54, JU55
JU50, JU51
JU46, JU47
JU18, JU19
JU42, JU43
JU38, JU39
JU10, JU11
JU16, JU17
JU22, JU23
JU27, JU26
JU31, JU30
JU14, JU15
JU20, JU21
JU25, JU24
JU29, JU28
JU33, JU32
JU34, JU35
JU6, JU7
JU4, JU5
JU8, JU9
Power Supplies
RMS
Primary in-phase differential outputs from MSB to LSB. “+” indicates the true value,
“-” denotes the complementary outputs
Auxiliary in-phase differential outputs from MSB to LSB. “+” indicates the true
value, “-” denotes the complementary outputs
Primary quadrature differential outputs from MSB to LSB. “+” indicates the true
value, “-” denotes the complementary outputs
Auxiliary quadrature differential outputs from MSB to LSB. “+” indicates the true
value, “-” denotes the complementary outputs
Out-of-range signal’s true and complementary outputs
Data Ready LVDS output latch clock. Output data changes on the rising edge of
DREADY+
. The typical
Clock
MAX105 Evaluation Kit
(400MHz for MAX107).
The input signals are AC-coupled. The DC biasing level
is internally set to the reference voltage V
MAX105’s analog input resistance is 2kΩ per input.
However, the EV kit’s I/Q input resistance is set to 50Ω
by an external resistor. For single-ended operation,
apply a signal to one of the analog inputs and terminate
the opposite complimentary input with a 50Ω resistor to
ground.
Note: When a differential signal is applied to the ADC,
the positive and negative input pins of the ADC each
receive half of the input signal supplied to the balun. A
common mode voltage of +2.5V is established within
the part and blocked by the AC-coupling capacitors.
FUNCTIONAL DESCRIPTION
I/Q Input Signals
REF
. The
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