NCP5425SOEVB ON Semiconductor, NCP5425SOEVB Datasheet - Page 19
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NCP5425SOEVB
Manufacturer Part Number
NCP5425SOEVB
Description
EVAL BOARD FOR NCP5425SO
Manufacturer
ON Semiconductor
Specifications of NCP5425SOEVB
Design Resources
NCP5425SOEVB BOM NCP5425SOEVB Gerber Files NCP5425SOEVB Schematic
Main Purpose
DC/DC, Step Down
Outputs And Type
1, Non-Isolated
Voltage - Output
0.8V
Current - Output
30A
Voltage - Input
4.6 ~ 12 V
Regulator Topology
Buck
Frequency - Switching
300kHz
Board Type
Fully Populated
Utilized Ic / Part
NCP5425
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power - Output
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
NCP5425SO
Other names
NCP5425SOEVBOS
simultaneous equations:
Example 2
from the Master controller, and 33.3% from the Slave.
Figure 13 shows the configuration of the inductor sense
networks and Slave error amplifier for this case. The ratio of
Master−to−Slave load current is equal to 66.7%/33.3%, or
2:1. Therefore R2 and R3 must be chosen to satisfy two
conditions:
value of R1, Cf can be calculated as follows:
f = operating frequency of the controller
the RC time constant must be considered.
The values of R2 and R3 can be found by solving two
Solving for R2 and R3 yields:
Assume we have elected to source 66.7% output current
A parallel equivalent resistance equal to R1, and,
A ratio such that the drop across the parasitic resistance of
the Master inductor is 2 times the drop across the parasitic
resistance of the Slave inductor when the inputs to the
Slave error amplifier are equal (assumes the inductors are
identical). The optimum value of R1 is described by the
equation:
With the value of R
When a filter is added, the response delay introduced by
Q1
Q2
R2 + R3 2
R1 + (R2 * R3) (R2 ) R3)
Cf + 1 (2p · f · R F ), where :
Error Amp
Master
R2 + 1.5R1
R3 + 3R1
R1 + Lx (C1 * Rx)
Figure 14. Addition of a Low Pass Filter to the Current Sense Reference Input
F
set to approximately two times the
−
+
Vfb1
0.8 V Ref.
Internal
R1
L1
C1
http://onsemi.com
R3
R3
R4
NCP5425
Vout
Vin
19
simultaneous equations:
single output design. This disables the internal Error
Amplifier Reference clamp, and increases its common mode
range.
No Load Zero Balance
inserted between the Master controller inductor sensing RC
network and the Slave controller Vref2 input pin (see
Figure 14). This will attenuate the amplitude of the
out−of−phase ripple current signal superimposed on the DC
current signal, providing a smoother Slave Error Amplifier
reference input.
Configuring a Dual Output Application
•
•
C3
The values of R2 and R3 can be found by solving two
Solving for R2 and R3 yields:
Note that the Mode pin must be floating for a two−phase,
To improve current matching, a low pass filter can be
To configure the NCP5425 for a dual output application:
The Mode pin must be grounded
An external voltage reference must be provided for
Controller 2, via the Vref2 pin
Low Pass
Filter
R
F
C2
R2 + R3
R1 + (R2 * R3) (R2 ) R3)
L2
R2 + 2R1
R3 + 2R1
Vfb2
Vref2
R2
C
F
+
−
Error Amp
Slave
Q3
Q4