LM3207TLEV National Semiconductor, LM3207TLEV Datasheet - Page 5

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LM3207TLEV

Manufacturer Part Number
LM3207TLEV
Description
BOARD EVALUATION LM3207TL
Manufacturer
National Semiconductor
Series
PowerWise®r
Datasheets

Specifications of LM3207TLEV

Main Purpose
DC/DC, Step Down with LDO
Outputs And Type
1, Non-Isolated
Voltage - Output
0.8 ~ 3.6V, 2.875V
Current - Output
650mA, 10mA
Voltage - Input
2.7 ~ 5.5V
Regulator Topology
Buck
Frequency - Switching
2MHz
Board Type
Fully Populated
Utilized Ic / Part
LM3207
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power - Output
-
Board Layout Considerations
The LM3207 converts higher input voltage to lower output
voltage with high efficiency. This is achieved with an inductor-
based switching topology. During the first half of the switching
cycle, the internal PMOS switch turns on, the input voltage is
applied to the inductor, and the current flows from P
the output capacitor (C2) through the inductor. During the
second half cycle, the PMOS turns off and the internal NMOS
turns on. The inductor current continues to flow via the induc-
tor from the device PGND line to the output capacitor (C2).
The inductor current continues to flow via the inductor from
the device PGND line to the output capacitor (C2) .
Referring to Figure 5, the LM3207 has two major current loops
where pulse and ripple current flow. The loop shown in the
left hand side is important because pulse current flows in this
path. In the loop on the right hand side, the current waveform
in this path is triangular. Pulse current has many high-fre-
quency components due to fast di/dt. Triangular ripple current
also has wide high-frequency components. Board layout and
circuit pattern design of these two loops are key factors for
FIGURE 5. Current Loop
VIN
20200301
line to
5
reducing noise radiation and achieving stable operation. Oth-
er lines, such as input and output terminals are DC current,
therefore pattern width (current capability) and DCR drop
considerations are needed.
BOARD LAYOUT FLOW
1.
2.
3.
4.
5.
6.
7.
Note: The evaluation board shown in Figure 2 and Figure 3 for the LM3207
Minimize C1, PV
be as wide and short as possible. This is most important.
Minimize L1, C2, SW and PGND loop. These traces also
should be wide and short. This is the second priority.
Above layout patterns should be placed on the
component side of the PCB to minimize parasitic
inductance and resistance due to via-holes. It may be a
good idea that the SW to L1 path is routed between C2
(+) and C2(-) land patterns. If vias are used in these large
current paths, multiple via-holes should be used if
possible.
Connect C1(-), C2(-) and PGND with wide GND pattern.
This pattern should be short, so C1(-), C2(-), and PGND
should be as close as possible. Then connect to a PCB
common GND pattern with as many via-holes as
possible.
SGND should not connect directly to PGND. Connecting
these pins under the device should be avoided. (If
possible, connect SGND to the common port of C1(-), C2
(-) and PGND.)
FB line should be protected from noise. It is a good idea
to use an inner GND layer (if available) as a shield.
The LDO Cap C7 should be placed as close to the PA as
possible and as far away from the switcher to suppress
high frequency switch noises.
was designed with the considerations mentioned above, and it shows
good performance. However some aspects have not been optimized
because of limitations due to evaluation-specific requirements. The
board can be used as a reference. For specific questions, please refer
to a National representative.
IN
, and PGND loop. These traces should
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