LP3906SQ-JXXIEV National Semiconductor, LP3906SQ-JXXIEV Datasheet
LP3906SQ-JXXIEV
Specifications of LP3906SQ-JXXIEV
Related parts for LP3906SQ-JXXIEV
LP3906SQ-JXXIEV Summary of contents
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... I2C compatible interface to allow a host controller access to the internal control registers of the LP3906. The LP3906 additionally features programmable power-on se- quencing and is offered in a tiny 0.8mm LLP-24 pin package. © 2007 National Semiconductor Corporation National Semiconductor Application Note 1532 Jonathan Guan February 2007 ...
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Evaluation Kit Setup Please use ESD protection to prevent any unwanted damag- ing ESD events! The LP3906 Evaluation Board should contain a USB interface to the left, as shown in Figure 1. Connect this setup to the USB port of ...
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Getting Started Because of internal pullups, the LP3906 should become ac- tive as soon as the USB cable is plugged in. To avoid dam- aging any parts, be sure to read the section describing how to power the board on ...
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FIGURE 4. LP3906 Evaluation Software User Interface 4 20210821 ...
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Using the Evaluation Software REGISTER INTERFACE A register control established through an I2C compatible se- rial interface allows the user to directly program the registers by writing to and reading from the memory map registers. This provides the user with ...
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REGULATOR OUTPUT VOLTAGE SELECTION The output voltages of all the LDO and buck converters can be programmed through I2C control registers by simply mov- ing the slider. The buck regulators have 2 sliders and a Hold/ Ramp button to control ...
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FIGURE 8. USB Interface ADC Jumpers 7 20210808 www.national.com ...
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BUCK AND EN_T CONTROL The Control / Status Bits Control menu controls the following aspects of the chip: 1. Temp – Reflects the status of the regulators buck or LDO regulator falls out of regulation because of the ...
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Using the Evaluation Hardware POWERING THE LP3906 BOARD We recommend that the user power the LP3906 through an external power supply if any loads are attached to the regu- lators. In case no external power supply is available (as for ...
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ENABLE CONFIGURATIONS THROUGH THE 20 PIN HEADER The following diagram shows how to enable or disable differ- ent regulators by jumpering pins in the 20 pin header. One practical use of grounding the enable pins of the regulators is to ...
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LP3906 HARDWARE BLOCK DESCRIPTION The evaluation board is fully populated with the LP3906. The LP3906 Evaluation board is designed to allow the user to test each function independently as well as in the system. Jumpers 1-6 as described in the ...
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JUMPER PURPOSE JP 1-6 These jumpers connect different Vins to the system VDD (VDD_M) JP1 connects Vin1 to VDD_M JP2 connects Vin2 to VDD_M JP3 connects the Buck core VDD to VDD_M JP4 connects VINLDO1 to VDD_M JP5 connects VINLDO12 ...
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FIGURE 12. LP3906 Evaluation Board Schematic 13 20210812 www.national.com ...
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Gerber Files The LP3906 is a four layer board. Below are the Gerber files for the board. The accompanying CD has the Gerber files in Cadence allegro format. www.national.com 20210813 20210815 14 20210814 20210816 ...
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PCB Layout Considerations The evaluation board layers from top to bottom are: 1. Top, component side 2. Ground plane 3. Mid signal section 4. Bottom, solder side For good performance of the circuit essential to place the input ...
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... SMD R11, R13 0 OHM 0603 SMD S1,S2 L2,L3 2 sat 2A 6x6mm 48 LLP package Power management IC Description C3216X7R1C106M C2012X7R1C105K C2012X7R1E474K MCR03EZPFX2202 MCR03EZPJ000 SMB Connector 131-1701-206 Buck boost inductor NP04SZB 2R2N LP3906 17 Vendor TDK TDK TDK Rohm Rohm Emerson Taiyo Yuden National Semiconductor www.national.com ...
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