LM5072EVAL National Semiconductor, LM5072EVAL Datasheet - Page 7

• Manufacturer Part Number: LM5072EVAL
• Description: BOARD EVALUATION LM5072
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM5072EVAL

• Main Purpose: Special Purpose DC/DC, Power Over Ethernet
• Outputs And Type: 1, Isolated
• Power - Output: 9.9W
• Voltage - Output: 3.3V
• Current - Output: 3A
• Voltage - Input: 38 ~ 60V
• Regulator Topology: Flyback
• Frequency - Switching: 250kHz
• Board Type: Fully Populated
• Utilized Ic / Part: LM5072
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Factors Limiting the Minimum
Operating Input Voltage
To optimize efficiency over the maximum input voltage range
of 10.5V to 60V (9V min seen at the VIN pin, after R1 and R2
are replaced with 1Ω), a larger magnetic core like the EFD20
should be used. The EFD20 core has adequate cross-
sectional area to handle the peak currents observed with a
10.5V input.
The effects of the current sense resistors R14 and R15 also
limit the minimum RAUX input operating voltage. The
LM5072’s internal slope compensation stabilizes the feed-
back loop of the dc-dc converter when the duty cycle ex-
ceeds 50% for input voltages lower than 22V. However, the
relative magnitude of the slope compensation is inversely
proportional to the values of R14 and R15. The maximum
values of R14 and R15 are governed by the following rela-
tion:
where
D
voltage;
f
L
k
V
V
Selecting 0.30Ω for both R14 and R15 will allow a minimum
operating voltage of 16V. For lower RAUX input voltages,
Dmax is greater and hence R14 and R15 must be reduced
accordingly. However, smaller resistors increase the effect of
internal slope compensation. Increasing the slope compen-
sating makes the feedback loop appear more like voltage
mode than current mode. This in turn requires the use of a
low ESR capacitor for C16, rather than the low cost capacitor
initially installed on the evaluation board.
In summary, the 16V minimum operating RAUX input voltage
of the evaluation board is limited by the low cost solution,
and also by the dropout of the startup regulator. In order to
use the evaluation board with a lower RAUX source, the
power transformer T1, the output capacitor C16, R14, and
R15 should be modified, in addition to the installation of D2.
D2 should be installed whenever the voltage at the VIN pin is
less than 15V. This ensures the V
voltage to start given its relatively high drop out requirement.
One must also be careful not to violate the VCC pin’s abso-
lute maximum voltage rating under this configuration. Ac-
cordingly, a 15V nominal auxiliary supply may be difficult to
design for, as it will require the installation of D2 and violate
the pin’s absolute maximum rating. Additional circuitry may
be required, or the selection of a different auxiliary input
voltage.
Performance Characteristics
PoE INPUT POWER UP SEQUENCE
The high level of integration designed into the LM5072 al-
lows all power sequencing communications to occur within
the IC. Very little system management design is required by
sw
m
t
o
F
max
the transformer’s primary to secondary turns ratio
the output voltage, in volts
the forward drop of the output diode D5, in volts
the switching frequency, in kHz
the flyback transformer primary inductance, in µH
is the duty cycle at the minimum AUXILIARY input
CC
regulator has enough
(Continued)
7
the user. The power up sequence is as follows. Note that the
RTN pin (IC pin 8) is isolated from the +3.3V RTN output pin
of the board:
1. Before power up, all nodes in the non-isolated section of
2. The V
3. Once power good has been asserted, the SS (Soft-
4. As the switching regulator achieves regulation, the aux-
Figure 4 shows the voltage at the RTN pin (referenced to
VEE), output voltage V
startup sequence. The RTN voltage gradually drops as the
input current charges the input capacitors. When the charg-
ing process is completed, the RTN voltage drops to below
1.5V, followed by the soft start of the converter.
Figure 5 shows the V
about 8V is first produced by the internal startup regulator.
When the output regulation is established, V
about 11V through cross-regulation.
Horizontal Resolution: 5 ms/Div.
Trace 1: VOUT, 2V/Div.
Trace 2: RTN pin (referenced to VEE), 20V/Div.
Trace 3: Input Current, 200 mA/Div.
the power supply remain at high potential until UVLO is
released and the drain of the internal hot swap MOSFET
is pulled down to VEE (IC pin 7).
quence. During V
on the order of 20mA, but this will likely not be noticed by
the user. Once the RTN pin of the IC drops below 1.5V
(referenced to VEE), and the gate of the hot swap
MOSFET rises, power good is asserted by pulling the
nPGOOD pin low.
Start) pin is released. The SS pin will rise at a rate equal
to the SS current source, typically 10µA, divided by the
SS pin capacitance, C26.
iliary winding will raise the V
thus shutting down the internal regulator and increasing
efficiency.
FIGURE 4. Normal PoE input Startup Sequence
CC
regulator powers up during the inrush se-
CC
CC
OUT
voltage during startup. The V
regulator startup, it draws current
and input current during a normal
CC
voltage to about 11V,
CC
20187205
is elevated to
www.national.com
CC
of