LP3907SQ-JXQXEV National Semiconductor, LP3907SQ-JXQXEV Datasheet
LP3907SQ-JXQXEV
Specifications of LP3907SQ-JXQXEV
Related parts for LP3907SQ-JXQXEV
LP3907SQ-JXQXEV Summary of contents
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... LP3907. The LP3907 additionally features programmable power-on se- quencing and a tiny 0.8mm LLP 24–pin package. FIGURE 1. LP3907 Evaluation Board with Intergrated USB Interface © 2007 National Semiconductor Corporation National Semiconductor Application Note 1619 Jonathan Guan September 2007 ...
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Evaluation Kit Setup Please use ESD protection to prevent any unwanted damag- ing ESD events! The LP3907 Evaluation Board should contain a USB interface to the left, as shown in Figure 2. Connect this setup to the USB port of ...
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Getting Started Because of internal pullups, the LP3907 should become ac- tive as soon as the USB cable is plugged in. To avoid dam- aging any parts, be sure to read the section describing how to power the board on ...
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FIGURE 4. LP3907 Evaluation Software User Interface 4 30017721 ...
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Using the Evaluation Software REGISTER INTERFACE (DIRECT WRITE AND READ) A register control established through an I interface allows the user to directly program the registers by writing to and reading from the memory map registers. This provides the user ...
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REGULATOR OUTPUT VOLTAGE SELECTION The output voltages of all the LDO and buck converters can be programmed through control registers by simply mov- ing the slider. The buck regulators have 2 sliders and a Hold/ Ramp button ...
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FIGURE 8. USB Interface ADC Jumpers 7 30017708 www.national.com ...
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BUCK AND EN_T CONTROL The Control / Status Bits Control menu controls the following aspects of the chip: 1. Temp – Reflects the status of the regulators buck or LDO regulator falls out of regulation because of the ...
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Using the Evaluation Hardware POWERING THE LP3907 BOARD We recommend that the user power the LP3907 through an external power supply if any loads are attached to the regu- lators. In case no external power supply is available (as for ...
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ENABLE CONFIGURATIONS THROUGH THE 20 PIN HEADER The following diagram shows how to enable or disable differ- ent regulators by jumpering pins in the 20 pin header. One practical use of grounding the enable pins of the regula- tors is ...
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LP3907 HARDWARE BLOCK DESCRIPTION The evaluation board is fully populated with the LP3907. The LP3907 Evaluation board is designed to allow the user to test each function independently as well as in the system. Jumpers 1-6 as described in the ...
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JUMPER PURPOSE JP 1-6 These jumpers connect different Vins to the system VDD (VDD_M): JP1 connects VIN1 to VDD_M JP2 connects VIN2 to VDD_M JP3 connects the Buck core VDD to VDD_M JP4 connects VINLDO1 to VDD_M JP5 connects VINLDO12 ...
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FIGURE 12. LP3907 Evaluation Board Schematic 13 30017714 www.national.com ...
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Gerber Files The LP3907 is a four layer board. Below are the Gerber files for the board. The accompanying CD has the Gerber files in Cadence allegro format. www.national.com 30017715 30017717 30017719 14 30017716 30017718 30017720 ...
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PCB Layout Considerations The evaluation board layers from top to bottom are: 1. Top, component side 2. Ground plane 3. Mid signal section 4. Bottom, solder side For good performance of the circuit essential to place the input ...
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