CDB4344 Cirrus Logic Inc, CDB4344 Datasheet - Page 12

• Manufacturer Part Number: CDB4344
• Description: BOARD EVAL FOR CS4344 DAC
• Manufacturer: Cirrus Logic Inc
• Series: Popguard®r

Specifications of CDB4344

• Number Of Dac's: 2
• Number Of Bits: 24
• Outputs And Type: 2, Single Ended
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 85°C
• Utilized Ic / Part: CS4344
• Description/function: Audio D/A
• Operating Supply Voltage: 5 V
• Product: Audio Modules
• For Use With/related Products: CS4344
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1006

12
4. APPLICATIONS
The CS4344 family accepts data at standard audio sample rates including 48, 44.1 and 32 kHz in SSM, 96, 88.2
and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via the serial data input pin (SDIN).
The Left/Right Clock (LRCK) determines which channel is currently being input on SDIN, and the optional Serial
Clock (SCLK) clocks audio data into the input data buffer. The CS4344/5/6/8 differ in serial data formats as shown
in
4.1
4.2
4.2.1
4.2.2
LRCK
Mode
(kHz)
176.4
44.1
88.2
Figures
128
192
32
48
64
96
Master Clock
MCLK/LRCK must be an integer ratio as shown in
cy at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio and speed
mode is detected automatically during the initialization sequence by counting the number of MCLK transi-
tions during a single LRCK period and by detecting the absolute speed of MCLK. Internal dividers are set
to generate the proper clocks.
MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK, LRCK and
SCLK must be synchronous.
Serial Clock
The serial clock controls the shifting of data into the input data buffers. The CS4344 family supports both
external and internal serial clock generation modes. Refer to
12.2880 18.4320
11.2896 16.9344
External Serial Clock Mode
The CS4344 family will enter the External Serial Clock Mode when 16 low to high transitions are detected
on the DEM/SCLK pin during any phase of the LRCK period. When this mode is enabled, the Internal Se-
rial Clock Mode and de-emphasis filter cannot be accessed. The CS4344 family will switch to Internal Se-
rial Clock Mode if no low to high transitions are detected on the DEM/SCLK pin for 2 consecutive frames
of LRCK. Refer to
Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK and
LRCK. The SCLK/LRCK frequency ratio is either 32, 48, 64, or 72 depending upon data format. Operation
in this mode is identical to operation with an external serial clock synchronized with LRCK. This mode al-
lows access to the digital de-emphasis function. Refer to
8.1920
7-10.
64x
-
-
-
-
-
-
12.2880
96x
-
-
-
-
-
-
QSM
Figure
12.2880
22.5792
24.5760
11.2896
8.1920
128x
-
-
-
-
12.
Table 1. Common Clock Frequencies
Table 1
12.2880
16.9344
18.4320
33.8680
36.8640
192x
-
-
-
-
illustrates several standard audio sample rates and the required
11.2896
12.2880
22.5792
24.5760
32.7680
8.1920
256x
MCLK (MHz)
-
-
-
Table
DSM
12.2880
16.9344
18.4320
33.8680
36.8640
49.1520
1. The LRCK frequency is equal to Fs, the frequen-
384x
-
-
-
Figures 7
Figures 7-10
22.5792
24.5760
32.7680
512x
-
-
-
-
-
-
-
12
for details.
for data formats.
33.8680
36.8640
49.1520
768x
-
-
-
-
-
-
SSM
32.7680
45.1580
49.1520
CS4344/5/6/8
1024x
-
-
-
-
-
-
DS613F1
36.8640
1152x
-
-
-
-
-
-
-
-