EVAL-AD5371EBZ Analog Devices Inc, EVAL-AD5371EBZ Datasheet
EVAL-AD5371EBZ
Specifications of EVAL-AD5371EBZ
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EVAL-AD5371EBZ Summary of contents
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FEATURES 40-channel DAC in 80-lead LQFP and 100-ball CSP_BGA Guaranteed monotonic to 14 bits Maximum output voltage span of 4 × V Nominal output voltage span of − Multiple, independent output voltage spans available System calibration ...
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AD5371 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 Performance Specifications......................................................... 4 AC Characteristics........................................................................ 5 Timing Characteristics ................................................................ 6 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. ...
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GENERAL DESCRIPTION 1 The AD5371 contains 40 14-bit DACs in a single 80-lead LQFP or 100-ball CSP_BGA. The device provides buffered voltage outputs with a span of 4× the reference voltage. The gain and offset of each DAC can be ...
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AD5371 SPECIFICATIONS PERFORMANCE SPECIFICATIONS open circuit; gain (M), offset (C), and DAC offset registers at default values; temperature range for the ...
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Parameter LVDS INTERFACE (REDUCED RANGE LINK) 2 Digital Inputs Input Voltage Range Input Differential Threshold External Termination Resistance Differential Input Voltage POWER REQUIREMENTS Power Supply Sensitivity ∆Full Scale/∆V DD ∆Full Scale/∆V SS ∆Full ...
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AD5371 TIMING CHARACTERISTICS open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T L Table ...
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Circuit and Timing Diagrams 2.2k Ω TO OUTPUT PIN C L 50pF Figure 2. Load Circuit for BUSY Timing Diagram SCLK SYNC 5 DB23 SDI BUSY 1 LDAC 1 VOUTx 2 LDAC ...
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AD5371 SCLK SYNC SDI DB23 SDO SYNC SYNC t 3 SCLK SCLK MSB D23 SDI SDI DB0 DB23 INPUT WORD SPECIFIES REGISTER TO BE READ DB0 DB23 SELECTED REGISTER DATA CLOCKED OUT LSB FROM PREVIOUS WRITE ...
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ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents not cause SCR latch-up. Table 6. Parameter V to AGND AGND DGND CC Digital Inputs to ...
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AD5371 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS LDAC 1 CLR 2 RESET 3 BUSY 4 TESTI 5 VOUT27 6 SIGGND3 7 VOUT28 8 VOUT29 9 VOUT30 10 VOUT31 11 VOUT32 12 VOUT33 13 VOUT34 14 VOUT35 15 SIGGND4 16 VOUT36 17 ...
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DGND DGND DV VOUT6 VOUT7 DV VOUT4 VOUT5 VOUT3 SIGGND0 VOUT1 VOUT2 VOUT0 NC VREF0 NC VOUT23 VREF2 VOUT21 VOUT22 VOUT20 VOUT19 V VOUT17 SIGGND2 DD V VOUT18 VOUT16 DD Table 7. Pin Function Descriptions Pin No. Ball ...
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AD5371 Pin No. Ball No. Mnemonic 58 D11 SIGGND0 31 L7 SIGGND1 41 L12 SIGGND2 7 F1 SIGGND3 16 L3 SIGGND4 52 G12 VREF0 21 M4 VREF1 50 H11 VREF2 19 J9, L11 M12 20, ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0.50 0.25 0 –0.25 –0.50 0 4096 8192 DAC CODE Figure 9. Typical INL Plot –0.6 –0.3 0 INL (LSB) Figure 10. Typical INL Distribution 1.0 0.5 0 –0.5 ...
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AD5371 600 500 400 300 200 100 FREQUENCY (Hz) Figure 15. Output Noise Spectral Density 0. –12V +12V DD VREF = +3V 0. +5.5V CC 0.40 0.35 DV ...
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TERMINOLOGY Integral Nonlinearity (INL) Integral nonlinearity, or endpoint linearity measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function measured after adjusting for zero-scale error and full-scale error ...
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AD5371 THEORY OF OPERATION DAC ARCHITECTURE The AD5371 contains 40 DAC channels and 40 output amplifiers in a single package. The architecture of a single DAC channel consists of a 14-bit resistor-string DAC followed by an output buffer amplifier. The ...
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A/B REGISTERS AND GAIN/OFFSET ADJUSTMENT Each DAC channel has seven data registers. The actual DAC data-word can be written to either the X1A or the X1B input register, depending on the setting of the A /B bit in the control ...
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AD5371 OUTPUT AMPLIFIER The output amplifiers can swing to 1.4 V below the positive supply and 1.4 V above the negative supply, which limits how much the output can be offset for a given reference voltage. For example ...
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Reference Selection Example If Nominal output range = 12 V (− Zero-scale error = ±70 mV Gain error = ±3%, and SIGGNDx = AGND = 0 V Then Gain error = ±3% => Maximum positive gain ...
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AD5371 RESET FUNCTION The reset function is initiated by the RESET pin. On the rising edge of RESET , the AD5371 state machine initiates a reset sequence to reset the X, M, and C registers to their default values. This ...
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TOGGLE MODE The AD5371 has two X2 registers per channel, X2A and X2B, that can be used to switch the DAC output between two levels with ease. This approach greatly reduces the overhead required by a microprocessor, which would otherwise ...
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AD5371 SERIAL INTERFACE The AD5371 contains two high speed serial interfaces: an SPI- compatible interface operating at clock frequencies MHz (20 MHz for read operations) and an LVDS interface. To minimize both the power consumption of the ...
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SPI READBACK MODE The AD5371 allows data readback via the serial interface from every register directly accessible to the serial interface, that is, all registers except the X2A, X2B, and DAC data registers. To read back a register ...
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AD5371 Table 15 shows which groups and which channels are addressed for every combination of Address Bit A5 to Address Bit A0. Table 15. Group and Channel Addressing Address Bit A2 to Address Bit A0 000 001 000 All groups, ...
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SPECIAL FUNCTION MODE If the mode bits are 00, the special function mode is selected, as shown in Table 16. Bit I21 to Bit I16 of the serial data-word select the special function, and the remaining bits are data required ...
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AD5371 Table 18. Address Codes for Data Readback F15 F14 F13 F12 ...
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APPLICATIONS INFORMATION POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. Design the PCB on which the AD5371 is mounted so that the ...
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... AD5371BSTZ-REEL −40°C to +85°C 1 AD5371BBCZ −40°C to +85°C 1 AD5371BBCZ-REEL −40°C to +85°C 1 EVAL-AD5371EBZ RoHS Compliant Part. ©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 0.75 1.60 0.60 MAX ...